MPC8540 datasheet(108/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

1-14

Freescale Semiconductor

Overview

The L2 cache tags are non-blocking for efficient load/store and snooping operations. The L2 cache

can be accessed internally while a load miss is pending (allowing hits under misses). Subsequent

to a load miss updating the memory, loads or stores can occur to that line on the very next cycle.

The L2 status array maintains status bits for each line to determine the status of the line. Different

combinations of these bits result in different L2 states. Note that because the cache is always

write-through, there is no modified state. The status bits include the following:

•

V—Valid

•

IL—Instruction locked

•

DL—Data locked

All accesses to the L2 memory are fully pipelined so back-to-back loads and stores can have

single-cycle throughput.

The cache can be configured to allocate instructions-only, data-only, or both. It can also be

configured to allocate global I/O writes that correspond to a programmable address window or that

use a special transaction type (stashing). In this way, DMA engines or I/O devices can force data

into the cache.

Line locks can be set in a variety of ways. The Book E architecture defines instructions that

explicitly set and clear locks in the L2. These instructions are supported by the core complex and

the L2 controller. In addition, the L2 controller can be configured to lock all lines that fall into

either of two specified address ranges when the line is allocated. Finally, the entire cache can be

locked by writing to a configuration register in the L2 cache controller.

The status array tracks line locks as either instruction locks or data locks for each line, and the

status array supports flash clearing of all instruction locks or data locks separately by writes to

configuration registers in the L2 controller.

1.3.3

e500 Coherency Module (ECM)

The e500 coherency module (ECM) provides a mechanism for I/O-initiated transactions to snoop

the bus between the e500 core and the integrated L2 cache in order to maintain coherency across

local cacheable memory. It also provides a flexible switch-type structure for core and I/O-initiated

transactions to be routed or dispatched to target modules on the device.

1.3.4

DDR SDRAM Controller

The MPC8540 supports DDR-I SDRAM that operates at up to 166 MHz (333-MHz data rate). The

memory interface controls main memory accesses and provides for a maximum of 3.5 Gbytes of

main memory. The memory controller can be configured to support the various memory sizes

through software initialization of on-chip configuration registers.

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