MPC8540 datasheet(106/1302 Pages) FREESCALE

106 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

1-12

Freescale Semiconductor

Overview

— Unified L2 MMU

– 16-entry, fully-associative TLB array for variable-sized pages

– 256-entry, two-way set-associative TLB for 4-Kbyte pages

— Software reload for TLBs

— Virtual memory support for as much as 4 Gbytes (2

32) of virtual memory

— Real memory support for as much as 4 Gbytes (2

32) of physical memory

— Support for big-endian and true little-endian memory on a per-page basis

•

Power management

— Low power, 1.2-V design

— Dynamic power management on the core minimizes power consumption of functional

units, such as execution units, caches, and MMUs, when they are idle.

— Core power-saving modes: core-halted and core-stopped

— NAP, DOZE, and SLEEP bits in HID0 that can be used to assert nap, doze, and sleep

core output signals to initiate power-saving modes at the integrated-device level

— Internal clock multipliers of 2x, 2.5x, and 3x from bus clock

•

Testability

— LSSD scan design

— JTAG interface

— ESP support

— ABIST for arrays

—LBIST

•

Reliability and serviceability

— Internal code parity

— Parity checking on e500 local bus

1.3.2

On-Chip Memory Unit

The MPC8540 contains an internal 256-Kbyte memory array that can be configured as

memory-mapped SRAM or as a look-aside L2 cache. The array can also be divided into two

128-Kbyte arrays, one of which may be used as cache and the other as SRAM.

The memory controller for this array connects to the core complex bus (CCB) and communicates

through 128-bit read and write buses to the e500 core and the MPC8540 system logic.

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