MPC8540 datasheet(107/1302 Pages) FREESCALE

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MPC8540 Architecture Overview

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

1-13

The on-chip memory unit contains:

•

256 Kbytes of on-chip memory

— L2 cache partitioning is configurable

– Can act as a 256-Kbyte L2 cache

–256-Kbyte array organized as 1024 8-way sets of 32-byte cache lines

– Array can be partitioned into 128-Kbyte L2 cache and 128-Kbyte memory mapped

SRAM

– Can act as two 128-Kbyte memory-mapped SRAM arrays or a 256-Kbyte SRAM

region

— SRAM operation is byte-accessible

— Data ECC on 64-bit boundaries (single-error correction, double-error detection)

— Tag parity (1 bit covering all tag bits)

— Cache mode supports instruction caching, data caching, or both

— External masters can force data to be allocated into the cache through programmed

memory ranges or special transaction types

— Separate locking for instructions and data so that locks can be set and cleared separately

— Supports locking the entire cache or selected lines

– Individual line locks are set and cleared through core-initiated instructions, by

external reads or writes, or by accesses to programmed memory ranges

— Flash clearing done through writes to L2 configuration registers

— Locks for the entire cache may be set and cleared by accesses to memory-mapped

control registers

1.3.2.1

On-Chip Memory as Memory-Mapped SRAM

When the on-chip memory is configured as an SRAM, the 256 Kbytes of memory can be

configured to reside at any aligned location in the memory map. It is byte-accessible and fully

ECC-protected, using read-modify-write transactions for sub-cacheline transactions. I/O devices

can access the SRAM by marking transactions global so that they are directed to the CCB.

1.3.2.2

On-Chip Memory as L2 Cache

The MPC8540 on-chip memory arrays include a 256-Kbyte data array, an address tag array, and a

status array.

The data array is organized as 1024 sets of 8 cache lines. Each cache line size is 32 bytes. The

replacement policy in each eight-way set is governed by a pseudo-LRU algorithm. The data is

protected with ECC, and the tag array is protected by parity.

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