MPC8540 datasheet(109/1302 Pages) FREESCALE

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MPC8540 Architecture Overview

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

1-15

The MPC8540 supports a variety of SDRAM configurations. SDRAM banks can be built using

DIMMs or directly-attached memory devices. Fifteen multiplexed address signals provide for

device densities of 64 Mbits, 128 Mbits, 256 Mbits, and 512 Mbits, and 1 Gbit. Four chip select

signals support up to four banks of memory. The MPC8540 supports bank sizes from 64 Mbytes

to 1 Gbyte. Nine column address strobes (MDM[0:8]) are used to provide byte selection for

memory bank writes.

The MPC8540 can be configured to retain the currently active SDRAM page for pipelined burst

accesses. Page mode support of up to 16 simultaneously open pages can dramatically reduce

access latencies for page hits. Depending on the memory system design and timing parameters,

using page mode can save 3 to 4 clock cycles from subsequent burst accesses that hit in an active

page.

The MPC8540 supports ECC for system memory. Using ECC, the MPC8540 detects and corrects

all single-bit errors and detects all double-bit errors and all errors within a nibble.

The MPC8540 can invoke a level of system power management by asserting the MCKE SDRAM

signal on-the-fly to put the memory into a low-power sleep mode.

1.3.5

Programmable Interrupt Controller (PIC)

The programmable interrupt controller (PIC) implements the necessary functions to provide a

flexible solution for a general-purpose interrupt control. The interrupt controller unit implements

the logic and programming structures of the OpenPIC architecture. The MPC8540 interrupt

controller unit supports its processor core and provides for 12 external interrupts (with fully nested

interrupt delivery), 4 message interrupts, internal-logic driven interrupts, and 4 global high

resolution timers. Up to 16 programmable interrupt priority levels are supported.

The interrupt controller unit can be bypassed to allow use of an external interrupt controller.

Inter-processor interrupt (IPI) communication is supported through the external interrupt and core

reset signals of different processor cores on the same device. The four IPIs are only used for

self-interrupt in a single-core device such as the MPC8540.

1.3.6

I2C Controller

The inter-IC (IIC or I

2C) bus is a two-wire, bidirectional serial bus that provides a simple and

efficient method of data exchange between devices. The synchronous, multiple-master bus of the

2C allows the MPC8540 to exchange data with other I2C devices, such as microcontrollers,

EEPROMs, real-time clock devices, A/D converters, and LCDs. The two-wire bus (serial data

SDA and serial clock SCL) minimizes the interconnections between devices. The synchronous,

multiple-master bus of the I

2C allows the connection of additional devices to the bus for expansion

and system development.

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