MPC8540 datasheet(114/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

1-20

Freescale Semiconductor

Overview

1.3.16 Clocking

The MPC8540 takes in the PCI_CLK/SYSCLK signal as an input to the device PLL and multiplies

it by an integer from 1 to 16 to generate the core complex bus clock (the platform clock), which

operates at the same frequency as the DDR DRAM data rate (for example, 266 or 333 MHz). The

L2 cache also operates at this frequency. The e500 core uses the CCB clock as an input to its PLL,

which multiplies it again by 2, 2.5, 3, or 3.5 to generate the core clock.

DLLs are used in the DDR SDRAM controller and the local bus memory controller (LBC) to

generate memory clocks. Six differential clock pairs are generated for DDR SDRAMs. Two clock

outputs are generated for the LBC.

The RapidIO transmit clock may be sourced from one of three locations: the platform clock, the

RapidIO receive clock, or a special differential clock input. This input is designed to receive inputs

from an external clock synthesis device driving a clock with a frequency of up to 500 MHz.

1.3.17 Address Map

The MPC8540 supports a flexible physical address map. Conceptually, the address map consists

of local space and external address space. The local address map is 4 Gbytes. The MPC8540 can

be made part of a larger system address space through the mapping of translation windows. This

functionality is included in the address translation and mapping units (ATMUs). Both inbound and

outbound translation windows are provided. The ATMUs allows the MPC8540 to be part of larger

address maps such as the PCI 64-bit address environment and the RapidIO environment.

1.3.18 OCeaN Switch Fabric

In order to reduce the strain on the core interconnects with the addition of new functional blocks

in this generation of the PowerQUICC family, an on-chip non-blocking crossbar switch fabric

called OCeaN (on-chip network) has been integrated to decrease contention, decrease latency, and

increase bandwidth. This revolutionary non-blocking crossbar fabric allows for full-duplex port

connections at 128 Gbps concurrent throughput and independent per-port transaction queuing and

flow control.

1.3.19 Processing Across the On-Chip Fabric

When processing across the on-chip fabric, the ATMUs at each fabric port are used to determine

the flow of data across the MPC8540. The ATMUs at each fabric port are responsible for

generating a fabric port destination ID as well as a new local device address. The port ID and local

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