MPC8540 datasheet(105/1302 Pages) FREESCALE

105 / 1302 page

MPC8540 Architecture Overview

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

1-11

•

Cache coherency

— Bus support for hardware-enforced coherency (bus snooping)

•

Core complex bus (CCB)

— High-speed, on-chip local bus with data tagging

— 32-bit address bus

— 60x-like address protocol with address pipelining and retry/copyback

— Two general-purpose read data, one write data bus

— 128-bit data plus parity/tags (each data bus)

— Supports out-of-order reads, in-order writes

— Little to no data bus arbitration logic required for native systems

— Easily adaptable to 60x-like environments

— Supports one-level pipelining of addresses with address-retry responses

•

Extended exception handling

— Supports Book E interrupt model

– Interrupt vector prefix register (IVPR)

– Vector offset registers (IVORs) 0–15 as defined in Book E, plus e500-defined IVORs

32–35

– Exception syndrome register (ESR)

– Book E–defined preempting critical interrupt, including critical interrupt status

registers (CSRR0 and CSRR1) and an rfci instruction

— e500-specific interrupts not defined in Book E architecture

– SPE APU unavailable exception

– Floating-point data exception

– Floating-point round exception

– Performance monitor

•

Memory management unit (MMU)

— Data L1 MMU

– Four-entry, fully-associative TLB array for variable-sized pages

– 64-entry, four-way set-associative TLB for 4-Kbyte pages

— Instruction L1 MMU

– Four-entry, fully-associative TLB array for variable-sized pages

– 64-entry, four-way set-associative TLB for 4-Kbyte pages

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