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MPC8540 датащи(PDF) 103 Page - Freescale Semiconductor, Inc |
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MPC8540 датащи(HTML) 103 Page - Freescale Semiconductor, Inc |
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103 / 1302 page ![]() MPC8540 Architecture Overview MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 1-9 NOTE The SPE APU and SPFP APU functionality will be implemented in the MPC8540, the MPC8560 and in their derivatives (that is, in all PowerQUICC III devices). However, these instructions will not be supported in devices subsequent to PowerQUICC III. Freescale Semiconductor strongly recommends that use of these instructions be confined to libraries and device drivers. Customer software that uses SPE or SPFP APU instructions at the assembly level or that uses SPE intrinsics will require rewriting for upward compatibility with next-generation PowerQUICC devices. Freescale Semiconductor offers a libmoto_e500 library that uses SPE and SPFP APU instructions. Freescale will also provide future libraries to support next generation PowerQUICC devices. • L1 cache structure — 32-Kbyte, 32-byte line, eight-way set-associative instruction cache — 32-Kbyte, 32-byte line, eight-way set-associative data cache — 1.5-cycle cache array access, 3-cycle load-to-use latency — Pseudo-LRU replacement algorithm — Copy-back data cache • Dual-dispatch superscalar • Precise exception handling • Seven-stage pipeline control • Instruction unit — Twelve-entry instruction queue — Full hardware detection of interlocks — Dispatch up to two instructions per cycle — Dispatch serialization control — Register dependency resolution and renaming • Branch unit (BU) — Dynamic branch prediction — Two-entry branch instruction queue (BIQ) — Executes all branch and CR logical instruction • Completion unit — As many as 14 instructions allowed in 14-entry completion queue — In-order retirement of up to two instructions per cycle |
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