MPC8540 datasheet(129/1302 Pages) FREESCALE

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Configuration, Control, and Status Register Map

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

2-11

2.3.1

Accessing CCSR Memory from External Masters

In addition to being accessible by the e500 processor, the configuration, control, and status

registers are accessible from external interfaces. This allows external masters on the I/O ports to

configure the MPC8540.

External masters do not need to know the location of the CCSR memory in the local address map.

Rather, they access this region of the local memory map through a window defined by a register

in the interface’s programming model that is accessible to the external master from its external

memory map.

The PCI base address for accessing the local CCSR memory is selectable through the PCI

configuration and status register base address register (PCSRBAR), at offset 0x10, described in

Section 16.3.2.11, “PCI Base Address Registers.” An external PCI master sets this register by

running a PCI configuration cycle to the MPC8540. Subsequent memory accesses by a PCI master

to the PCI address range indicated by PCSRBAR are translated to the local address indicated by

the current setting of CCSRBAR.

The RapidIO base address for accessing the local CCSR memory is selectable through the

RapidIO LCSBA1CSR, defined in the RapidIO programming model, see Section 17.3.1.12,

“Local Configuration Space Base Address 1 Command and Status Register (LCSBA1CSR).” An

external RapidIO master can set the value of LCSBA1CSR with a maintenance packet. Then

subsequent read and write packets whose RapidIO addresses match the window defined by

LCSBA1CSR are translated to the local address range indicated by CCSRBAR.

2.3.2

Organization of CCSR Memory

The configuration, control, and status registers of the MPC8540 are grouped according to

functional units. Most functional blocks are allocated for a 4-Kbyte address space for registers.

Registers that fall into this category are referred to as general utilities registers. These registers

occupy the first 256 Kbytes of CCSR memory.

Registers that control functions that are not particular to a functional unit but to the device as a

whole occupy the highest 256 Kbytes of CCSR memory. These are referred to as device-specific

registers.

Some functional units, such as RapidIO and the OpenPIC-based interrupt controller have larger

address spaces as defined by their programming models. The registers for these blocks are given

their own large regions of CCSR memory.

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