MPC8540 datasheet(125/1302 Pages) FREESCALE

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Address Translation and Mapping

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

2-7

2.2.3.4

Precedence of Local Access Windows

If two local access windows overlap, the lower numbered window takes precedence. For instance,

if two windows are setup as shown in Table 2-7, local access window 1 governs the mapping of

the 1-Mbyte region from 0x7FF0_0000 to 0x7FFF_FFF, even though the window described in

local access window 2 also encompasses that memory region.

2.2.3.5

Configuring Local Access Windows

Once a local access window is enabled, it should not be modified while any device in the system

may be using the window. Neither should a new window be used until the effect of the write to the

window is visible to all blocks that use the window. This can be guaranteed by completing a read

of the last local access window configuration register before enabling any other devices to use the

window. For instance, if local access windows 0–3 are being configured in order during the

initialization process, the last write (to LAWAR3) should be followed by a read of LAWAR3

8–11

TRGT_IF Identifies the target interface ID when a transaction hits in the address range defined by this

window. Note that configuration registers and SRAM regions are mapped by the windows defined

by CCSRBAR and L2SRBAR. These mappings supersede local access window mappings, so

configuration registers and SRAM do not appear as a target for local access windows.

0000 PCI/PCI-X

0001–0011Reserved

0100 Local bus memory controller

0101–1011Reserved

1100 RapidIO

1101–1110Reserved

1111 DDR SDRAM

12–25

—

Write reserved, read = 0

26–31

SIZE

Identifies the size of the window from the starting address. Window size is 2(SIZE+1) bytes.

000000–001010Reserved

001011 4 Kbytes

001100 8 Kbytes

00110116 Kbytes

. . . . . . . 2(SIZE+1) bytes

011110 2 Gbytes

011111–111111 Reserved

Table 2-7. Overlapping Local Access Windows

Window

Base Address

Size

Target Interface

0x7FF0_0000

1 Mbyte

0b0100 (Local bus controller —LBC)

0x0000_0000

2 Gbytes

0b1111 (DDR SDRAM)

Table 2-6. LAWARn Field Descriptions (continued)

Bits

Name

Description

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