MPC8540 datasheet(122/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

2-4

Freescale Semiconductor

Memory Map

window, if address translation is being performed, the new translated address is created by

concatenating the window offset to the translation address. Again, the windows size attribute

dictates how many bits are translated.

2.2.1

SRAM Windows

The on-chip memory array of the MPC8540 can be configured as a memory-mapped SRAM of

128 or 256 Kbytes. Configuration registers in the L2 cache controller set the base addresses and

sizes for these windows. When enabled, these windows supersede all other mappings of these

addresses for processor and global (snoopable) I/O transactions. Therefore, SRAM windows must

never overlap configuration space as defined by CCSRBAR. It is possible to have SRAM

windows overlap local access windows, but this is discouraged because processor and snoopable

I/O transactions would map to the SRAM while non-snooped I/O transactions would be mapped

by the local access windows. Only if all accesses to the SRAM address range are snoopable can

results be consistent if the SRAM window overlaps a local access window.

See Section 7.3.1.4, “L2 Memory-Mapped SRAM Base Address Registers 0–1 (L2SRBARn),”

for information about configuring SRAM windows.

2.2.2

Window into Configuration Space

CCSRBAR defines a window used to access all memory-mapped configuration, control, and

status registers. No address translation is done, so there are no associated translation address

registers. The window is always enabled with a fixed size of 1 Mbyte; no other attributes are

attached, so there is no associated size/attribute register. This window always takes precedence

over all local access windows. See Section 4.3.1.1.2, “Configuration, Control, and Status Base

Address Register (CCSRBAR),” and Section 2.3, “Configuration, Control, and Status Register

Map.”

2.2.3

Local Access Windows

As demonstrated in the address map overview in Section 2.1, “Local Memory Map Overview and

Example,” local access windows associate a range of the local 32-bit address space with a

particular target interface. This allows the internal interconnections of the MPC8540 to route a

transaction from its source to the proper target. No address translation is performed. The base

address defines the high order address bits that give the location of the window in the local address

space. The window attributes enable the window, define its size, and specify the target interface.

With the exception of configuration space (mapped by CCSRBAR), on-chip SRAM regions

(mapped by L2SRBAR registers), and default boot ROM, all addresses used by the system must

be mapped by a local access window. This includes addresses that are mapped by inbound ATMU

windows; target mappings of inbound ATMU windows and local access windows must be

consistent.

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