MPC8540 datasheet(119/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

2-1

Chapter 2

Memory Map

This chapter describes the MPC8540 memory map. An overview of the local address map is

followed by a description of how local access windows are used to define the local address map.

The inbound and outbound address translation mechanisms used to map to and from external

memory spaces are described next. Finally, the configuration, control, and status registers are

described, including a complete listing of all memory-mapped registers with cross references to

the sections detailing descriptions of each.

2.1

Local Memory Map Overview and Example

The MPC8540 provides an extremely flexible local memory map. The local memory map refers

to the 32-bit address space seen by the processor as it accesses memory and I/O space. DMA

engines also see this same local memory map. All memory accessed by the MPC8540 DDR

SDRAM and local bus memory controllers exists in this memory map, as do all memory-mapped

configuration, control, and status registers.

The local memory map is defined by a set of eight local access windows. Each of these windows

map a region of memory to a particular target interface, such as the DDR SDRAM controller or

the PCI controller. Note that the local access windows do not perform any address translation. The

size of each window can be configured from 4 Kbytes to 2 Gbytes. The target interface is specified

using the codes shown in Table 2-1.

Table 2-1. Target Interface Codes

Target Interface

Target Code

PCI/PCI-X

0000

Local bus

0100

RapidIO

1100

DDR SDRAM

1111

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