MPC8540 datasheet(200/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

4-14

Freescale Semiconductor

Reset, Clocking, and Initialization

4.4.3.3

Boot ROM Location

The first instruction executed by the e500 core is always address 0xFFFF_FFFC, which must be

a branch to an address within the 4-Kbyte boot page. The MPC8540 defines the default boot ROM

address range to be 8 Mbytes at address 0xFF80_0000 to 0xFFFF_FFFF. However, which on-chip

peripheral handles these boot ROM accesses can be selected at power up.

The boot ROM location inputs, shown in Table 4-11, establish the location of boot ROM. Accesses

to the boot vector and the default boot ROM region of the local address map are directed to the

interface specified by these inputs.

Note that the values latched on these signals during POR are accessible through the

memory-mapped PORBMSR (POR boot mode status register) described in Section 18.4.1.2,

“POR Boot Mode Status Register (PORBMSR).”

See Section 2.1, “Local Memory Map Overview and Example,” for an example memory map that

relies on the default boot ROM values. Also, see Section 4.3.1.3.1, “Boot Page Translation

affects CPU accesses to 0xFFF_Fnnn.

4.4.3.4

Host/Agent Configuration

The host/agent reset configuration inputs, shown in Table 4-12, configure the MPC8540 to act as

a host or as an agent of a master on another interface. In host mode, the MPC8540 is immediately

enabled to master transactions to the RapidIO and PCI interfaces. If the MPC8540 is an agent on

the RapidIO or the PCI interfaces, then the MPC8540 is disabled from mastering transactions on

that interface until the external host enables it to do so. The external host does this by setting the

control registers of the MPC8540’s interfaces appropriately. See details in the PCI and RapidIO

programming models described in Chapter 16, “PCI/PCI-X Bus Interface,” and Chapter 17,

“RapidIO Interface,” respectively.

Table 4-11. Boot ROM Location

Functional Signals

Reset Configuration

Name

Value

(Binary)

Meaning

TSEC1_TXD[6:4]

Default (111)

cfg_rom_loc[0:2]

000

PCI/PCI-X

001

DDR SDRAM

010

Reserved

011

RapidIO

100

Reserved

101

Local bus GPCM—8-bit ROM

110

Local bus GPCM—16-bit ROM

111

Local Bus GPCM—32-bit ROM (default)

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