MPC8540 datasheet(203/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

4-17

NOTE

While the width of both interfaces is controlled by this one

configuration input, the protocol (TBI or GMII) used by each is

separately controlled with other configuration inputs described in

Section 4.4.3.8, “TSEC1 Protocol,” and Section 4.4.3.9, “TSEC2

Protocol.”

4.4.3.8

TSEC1 Protocol

The TSEC1 protocol input, shown in Table 4-16, selects the protocol (GMII or TBI) used by the

TSEC1 controller. Note that the value latched on this signal during POR is accessible through the

memory-mapped PORDEVSR (POR device status register) described in Section 18.4.1.4, “POR

Device Status Register (PORDEVSR).”

4.4.3.9

TSEC2 Protocol

The TSEC2 protocol input, shown in Table 4-17, selects the protocol (GMII or TBI) used by the

TSEC2 controller. Note that the value latched on this signal during POR is accessible through the

memory-mapped PORDEVSR (POR device status register) described in Section 18.4.1.4, “POR

Device Status Register (PORDEVSR).”

Table 4-15. TSEC Width Configuration

Functiona

l Signal

Reset

Configuration

Name

Value

(Binary)

Meaning

EC_MDC

Default (1)

cfg_tsec_reduce

Ethernet interfaces operate in reduced mode, either RTBI or RGMII,

using only four transmit data signals and four receive data signals.

Ethernet interfaces operate in their standard TBI or GMII modes using

eight transmit data signals and eight receive data signals (default).

Table 4-16. TSEC1 Protocol Configuration

Functional

Signal

Reset

Configuration

Name

Value

(Binary

)

Meaning

TSEC1_TXD

Default (1)

cfg_tsec1

The TSEC1 controller operates using the GMII protocol (or RGMII if

configured in reduced mode as described in Section 4.4.3.7, “TSEC

Width”).

The TSEC1 controller operates using the TBI protocol (or RTBI if configured

in reduced mode as described in Section 4.4.3.7, “TSEC Width”) (default).

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