MPC8540 datasheet(196/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

4-10

Freescale Semiconductor

Reset, Clocking, and Initialization

NOTE

If the JTAG signals are not used, TRST may be tied inactive; however

it is recommended that TRST not remain asserted after the negation of

HRESET. TRST may be connected directly to HRESET.

There is no need to assert the SRESET signal when HRESET is

asserted. If SRESET is asserted upon negation of HRESET, the POR

sequence will be paused until SRESET is negated.

5. The MPC8540 enables I/O drivers.

6. The MPC8540 PCI/PCI-X interface can assert DEVSEL in response to configuration

cycles.

7. The e500 PLL configuration inputs are applied, allowing the e500 PLL to begin locking to

the device clock (the CCB clock).

8. The CCB clock is cycled for approximately 50

µs to lock the e500 PLL.

9. The internal hard reset to the e500 core is negated and soft resets are negated to the DLLs

and other remaining I/O blocks. The DLLs begin to lock.

10. When DLL locking is completed, the boot sequencer is released, causing it to load

configuration data from serial ROMs, if enabled, as described in Section 4.4.3.6, “Boot

Sequencer Configuration.”

11. When the boot sequencer completes, the RapidIO interface begins training, the PCI

interface is released to accept external requests, and the boot vector fetch by the e500 core

is allowed to proceed unless processor booting is further held off by POR configuration

inputs as described in Section 4.4.3.5, “CPU Boot Configuration.” The MPC8540 is now

in its ready state.

12. The ASLEEP signal negates synchronized to a rising edge of SYSCLK, indicating the

ready state. The ready state is also indicated by the assertion of READY/TRIG_OUT if

TOSR[SEL] = 000. In this case, READY is asserted with the same rising edge of

SYSCLK, to indicate that the device has reached its ready state. See Section 20.3.4.1,

“Trigger Out Source Register (TOSR),” for more information on this register.

Asserting READY allows external system monitors to know basic device status. For

example, exactly when it emerges from reset, or if the device is in a low-power mode. For

more information on the debug functions of TRIG_OUT, see Section 20.3.4, “Trigger Out

Function.” For more information about power management states, see Section 18.4.1,

“Register Descriptions.”

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