MPC8540 datasheet(202/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

4-16

Freescale Semiconductor

Reset, Clocking, and Initialization

4.4.3.6

Boot Sequencer Configuration

The boot sequencer configuration options, shown in Table 4-14, allow the boot sequencer to load

configuration data from the serial ROM located on the I2C port before the host tries to configure

the MPC8540. These options also specify normal or extended I

2C addressing modes. See

Section 11.4.5, “Boot Sequencer Mode,” for more information on the boot sequencer.

Note that the values latched on these signals during POR are accessible through the

memory-mapped PORBMSR (POR boot mode status register) described in Section 18.4.1.2,

“POR Boot Mode Status Register (PORBMSR).”

NOTE

When the boot sequencer is enabled, the processor core will be held in

reset and thus prevented from fetching boot code until the boot

sequencer has completed its task, regardless of the state of the CPU

boot configuration signal described in Section 4.4.3.5, “CPU Boot

Configuration.”

4.4.3.7

TSEC Width

The TSEC width input, shown in Table 4-15, selects standard versus reduced width for both of the

three-speed Ethernet controller interfaces. Note that the value latched on this signal during POR

is accessible through the memory-mapped PORDEVSR (POR device status register) described in

Section 18.4.1.4, “POR Device Status Register (PORDEVSR).”

Table 4-14. Boot Sequencer Configuration

Functiona

l Signals

Reset

Configuration

Name

Value

(Binary

)

Meaning

LGPL3,

LGPL5

Default

(11)

cfg_boot_seq[0:1]

Reserved

Normal I2C addressing mode is used. Boot sequencer is enabled and

loads configuration information from a ROM on the I2C interface. A valid

ROM must be present.

Extended I2C addressing mode is used. Boot sequencer is enabled and

loads configuration information from a ROM on the I2C interface. A valid

ROM must be present.

Boot sequencer is disabled. No I2C ROM is accessed (default).

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