MPC8540 datasheet(195/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

4-9

4.4.1.1

Soft Reset

Assertion of SRESET causes a machine check interrupt to the e500 core. When this occurs, the

soft reset flag is recorded in the machine check summary register (MCPSUMR) in the global

utilities block so that software can identify the machine check as a soft reset condition. See the

PowerPC™ e500 Core Complex Reference Manual for more information on the machine check

interrupt, and Section 18.4.1.13, “Machine Check Summary Register (MCPSUMR),” for more

information on the setting of the soft reset flag. Note that if SRESET is asserted before the e500

core is configured to handle a machine check interrupt, a core checkstop condition occurs, which

causes CKSTP_OUT to assert.

4.4.1.2

Hard Reset

The MPC8540 can be completely reset by the assertion of the HRESET input. The assertion of this

signal by external logic is the equivalent of a POR and causes the sequence of events described in

Section 4.4.2, “Power-On Reset Sequence.”

Refer to the MPC8540 Integrated Processor Hardware Specifications for the timing requirements

for HRESET assertion and negation.

The MPC8540 hard reset request output signal (HRESET_REQ) indicates to external logic that a

hard reset is being requested by hardware or a RapidIO device. Hardware causes this signal to

assert for a boot sequencer failure (see Section 11.4.5, “Boot Sequencer Mode,” and

Section 11.4.5.2, “EEPROM Data Format,”) or when the e500 watchdog timer is configured to

cause a reset request when it expires. A RapidIO device causes this signal to assert if it sends four

consecutive RapidIO link maintenance reset commands without any other intervening packets or

control symbols, except idle control symbols (see Section 17.4.1, “RapidIO Transaction, Packet,

and Control Symbol Summary,” for details of RapidIO transaction types).

4.4.2

Power-On Reset Sequence

The POR sequence for the MPC8540 is as follows:

1. Power is applied to meet the specifications in the MPC8540 Integrated Processor

Hardware Specifications.

2. System asserts HRESET and TRST causing all registers to be initialized to their default

states and most I/O drivers to be three-stated (some clock, clock enabled, and system

control signals are active).

3. System applies a stable SYSCLK signal and stable PLL configuration inputs, and the

device PLL begins locking to SYSCLK.

4. System negates HRESET after its required hold time and after POR configuration inputs

have been valid for at least 4 SYSCLK cycles.

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