MPC8540 datasheet(193/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

4-7

Table 4-7 defines ALTCAR fields.

4.3.1.3

Boot Page Translation

When the e500 core comes out of reset, its MMU has one 4-Kbyte page defined at 0xFFFF_Fnnn.

The first instruction executed by the e500 core is always address 0xFFFF_FFFC, which must be

a branch to an address within the 4-Kbyte boot page. For systems in which the boot code resides

at a different address, the MPC8540 provides boot page translation capability. Boot page

translation is controlled by the boot page translation register (BPTR). If enabled, this translation

affects CPU accesses to address range 0xFFFF_Fnnn.

The boot sequencer can enable boot page translation, or the boot page translation can be enabled

by an external host when the MPC8540 is configured to be in boot holdoff mode. If translation is

performed to a page outside of the default boot ROM address range defined in the MPC8540

(8 Mbytes at 0xFF80_0000 to 0xFFFF_FFFF as defined in Section 4.4.3.3, “Boot ROM

Location”), the external host or boot sequencer must also set up a local access window to define

the routing of the boot code fetch to the target interface that contains the boot code because the

BPTR defines only the address translation, not the target interface. See Section 2.1, “Local

Memory Map Overview and Example,” and Section 11.4.5, “Boot Sequencer Mode,” for more

information.

Table 4-7. ALTCAR Field Descriptions

Bits

Name

Description

Enable for a second configuration window. Like CCSRBAR, it has a fixed size of 1 Mbyte.

0 Second configuration window is disabled

1 Second configuration window is enabled

1–7

—

Write reserved, read = 0

8–11

TRGT_ID Identifies the device ID to target when a transaction hits in the 1-Mbyte address range defined by

the second configuration window.

0000 PCI/PCI-X interface

0001 Reserved

0010 Reserved

0011 Reserved

0100 Local bus controller

0101–0111Reserved

1000 Configuration, control, and status registers

1001–1011Reserved

1100 RapidIO

1101 Reserved

1110 Reserved

1111 Local memory —DDR SDRAM and on-chip SRAM

12–31

—

Write reserved, read = 0

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