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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8540 датащи(PDF) 185 Page - Freescale Semiconductor, Inc |
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MPC8540 датащи(HTML) 185 Page - Freescale Semiconductor, Inc |
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185 / 1302 page  Output Signal States During Reset MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 3-17 During reset, the MPC8540 ignores most input signals (except for the reset configuration signals) and drives most of the output-only signals to an inactive state. Table 3-4 shows the states of the output-only signals (that is, the signals that are not multiplexed with other inputs, or are not used as reset configuration signals during system reset). Table 3-4. Output Signal States During System Reset Interface Signal State During Reset DDR Memory MDM[0:8] High-Z DDR Memory MBA[0:1] High-Z DDR Memory MA[0:14] High-Z DDR Memory MWE High-Z DDR Memory MRAS High-Z DDR Memory MCAS High-Z DDR Memory MCS[0:3] High-Z DDR Memory MCKE[0:1] Driven Low DDR Memory MCK[0:5], MCK[0:5] High-Z RapidIO RIO_TCLK, RIO_TCLK Driven (toggling) RapidIO RIO_TD[0:7], RIO_TD[0:7] High-Z RapidIO RIO_TFRAME, RIO_TFRAME High-Z TSEC1 TSEC1_TXD[3:0] Input—reset config (test only) TSEC1 TSEC1_TX_EN Driven Low TSEC1 TSEC1_TX_ER High-Z TSEC1 TSEC1_GTX_CLK High-Z TSEC2 TSEC2_TXD[1:0] High-Z TSEC2 TSEC2_TX_EN Driven Low TSEC2 TSEC2_TX_ER High-Z TSEC2 TSEC2_GTX_CLK High-Z FEC FEC_TXD[0:3] High-Z FEC FEC_TX_EN Driven Low FEC FEC_TX_ER High-Z LBC LCLK[0:2] High-Z LBC LCS[0:5] High-Z LBC DMA_DACK2/LCS6 DMA_DDONE2/LCS7 High-Z LBC LBCTL Input—reset config (test only) DMA DMA_DACK[0:1] High-Z |
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