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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8540 датащи(PDF) 184 Page - Freescale Semiconductor, Inc |
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MPC8540 датащи(HTML) 184 Page - Freescale Semiconductor, Inc |
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184 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 3-16 Freescale Semiconductor Signal Descriptions 3.3 Output Signal States During Reset When a system reset is recognized (HRESET is asserted), the MPC8540 aborts all current internal and external transactions and releases all bidirectional I/O signals to a high-impedance state. See Chapter 4, “Reset, Clocking, and Initialization,” for a complete description of the reset functionality. Table 3-3. MPC8540 Reset Configuration Signals Functional Interface Functional Signal Name Reset Configuration Name Default PCI PCI_REQ64 cfg_pci_width 1 PCI_GNT4 cfg_pci_mode 1 PCI_GNT3 cfg_pci_debug 1 PCI_GNT2 cfg_pci_arbiter 1 PCI_GNT1 cfg_pci_impd 1 Ethernet Management EC_MDC cfg_tsec_reduce 1 TSEC1 TSEC1_TXD7 cfg_tsec1 1 TSEC1_TXD[6:4] cfg_rom_loc[0:2] 111 TSEC2 TSEC2_TXD7 cfg_tsec2 1 TSEC2_TXD[6:5] cfg_lb_hold[0:1] 11 TSEC2_TXD[4:2] cfg_dev_ID[7:5] 111 LBC LA27 cfg_cpu_boot 1 LA[28:31] cfg_sys_pll[0:3] Must be driven LWE[0:1]/LBS[0:1] cfg_pci_hold[0:1] 11 LWE[2:3]/LBS[2:3] cfg_host_agt0 cfg_host_agt1 11 LALE cfg_core_pll0 Must be driven LGPL0/LSDA10 cfg_rio_clk0 1 LGPL1/LSDWE cfg_rio_clk1 1 LGPL2/LOE/LSDRAS cfg_core_pll1 Must be driven LGPL3/LSDCAS cfg_boot_seq0 1 LGPL5/LSDAMUX cfg_boot_seq1 1 LAD[0:31] cfg_gpporcr Indeterminate if not driven (no default) Debug MSRCID0 cfg_mem_debug 1 MSRCID1 cfg_ddr_debug 1 |
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