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Configuration Signals Sampled at Reset

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

3-15

3.2

Configuration Signals Sampled at Reset

The signals that serve alternate functions as configuration input signals during system reset are

summarized in Table 3-3. The detailed interpretation of their voltage levels during reset is

described in Chapter 4, “Reset, Clocking, and Initialization.”

Note that throughout this document, the reset configuration signals are described as being sampled

at the negation of HRESET. However, there is a setup and hold time for these signals relative to

the rising edge of HRESET, as described in the MPC8540 Integrated Processor Hardware

Specifications. Note that the PLL configuration signals have different setup and hold time

requirements than the other reset configuration signals.

The reset configuration signals are multiplexed with other functional signals. The values on these

signals during reset are interpreted to be logic one or zero, regardless of whether the functional

signal name is defined as active-low. Most of the reset configuration signals have internal pull-up

resistors so that if the signals are not driven, the default value is high (a one), as shown in the table.

Some signals do not have pull-up resistors and must be driven high or low during the reset period.

For details about all the signals that require external pull-up resistors, see the MPC8540 Integrated

Processor Hardware Specifications.

Note that the multiplexing of various signals on the MPC8540 is controlled by the PMUXCR

TSEC2_TXD[6:5]

TSEC2 transmit data 6–5

TSEC2

cfg_lb_hold[0:1]

14-3/14-14

TSEC2_TXD7

TSEC2 transmit data 7

TSEC2

cfg_tsec2

14-3/14-14

TSEC2_TX_CLK

TSEC2 transmit clock in

TSEC2

—

14-3/14-14

TSEC2_TX_EN

TSEC2 transmit enable

TSEC2

—

14-3/14-14

TSEC2_TX_ER

TSEC2 transmit error

TSEC2

—

14-3/14-14

UART_CTS[0:1]

DUART clear to send

Dual UART

—

12-2/12-4

UART_RTS[0:1]

DUART ready to send

Dual UART

—

12-2/12-4

UART_SIN[0:1]

DUART serial data in

Dual UART

—

12-2/12-4

UART_SOUT[0:1]

DUART serial data out

Dual UART

—

12-2/12-4

UDE

Unconditional debug

event

PIC

—

10-6/10-8

Table 3-2. MPC8540 Alphabetical Signal Reference (continued)

Name

Description

Functional

Block

Alternate

Function(s)

No. of

Signals

I/O

Table/

Page

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