MPC8540 datasheet(188/1302 Pages) FREESCALE

188 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

4-2

Freescale Semiconductor

Reset, Clocking, and Initialization

4.2.1

System Control Signals

Table 4-2 describes some of the system control signals of the MPC8540. Section 4.4.3, “Power-On

Reset Configuration,” describes the signals that also function as reset configuration signals. Note

that the CKSTP_IN and CKSTP_OUT signals are described in Chapter 18, “Global Utilities.”

Table 4-2. System Control Signals—Detailed Signal Descriptions

Signal

Description

HRESET

Hard reset. Causes the MPC8540 to abort all current internal and external transactions and set

all registers to their default values. HRESET may be asserted completely asynchronously with

respect to all other signals.

State

Meanin

Asserted/Negated—See Chapter 3, “Signal Descriptions,” and Section 4.4.3,

“Power-On Reset Configuration,” for more information on the interpretation of the

other MPC8540 signals during reset.

Timing Assertion/Negation—The MPC8540 Integrated Processor Hardware Specifications

gives specific timing information for this signal and the reset configuration signals.

HRESET_RE

O Hard reset request. Indicates to the board (system in which the MPC8540 is embedded) that a

condition requiring the assertion of HRESET has been detected.

State

Meanin

Asserted—A watchdog timer, a RapidIO command, or a boot sequencer failure (see

Section 11.4.5, “Boot Sequencer Mode”) has triggered a request for hard reset.

Negated—Indicates no reset request

Timing Assertion/Negation—May occur anytime, synchronous to the core complex bus clock.

Once asserted, HRESET_REQ does not negate until HRESET is asserted.

SRESET

Soft reset. Causes a machine check interrupt to the e500 core. Note that if the e500 core is not

configured to process machine check interrupts, the assertion of SRESET causes a core

checkstop. SRESET need not be asserted during a hard reset.

State

Meanin

Asserted—Asserting SRESET causes a machine check interrupt (edge sensitive) to

the e500 core. SRESET has no effect while HRESET is asserted. However, the

POR sequence is paused if SRESET is asserted during POR.

Timing Assertion—May occur at any time, asynchronous to any clock

Negation—Must be asserted for at least two CCB_clk cycles

READY

O Ready. Multiplexed with TRIG_OUT. See Chapter 20, “Debug Features and Watchpoint Facility,”

for more information on TOSR and TRIG_OUT.

State

Meanin

Asserted—Indicates that the MPC8540 has completed the reset operation and is not

in a power-down state (nap, doze or sleep) when TOSR[SEL] equals 0b000. See

Section 4.4.2, “Power-On Reset Sequence,” for more information.

Timing Assertion/Negation—Initial assertion of READY after reset is synchronous with

SYSCLK. Subsequent assertion/negation due to power down modes occurs

asynchronously.

MPC8540 датащи(PDF) 188 Page - Freescale Semiconductor, Inc

MPC8540 датащи(HTML) 188 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL