MPC8540 datasheet(189/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

4-3

4.2.2

Clock Signals

Table 4-3 describes the overall clock signals of the MPC8540. Note that some clock signals are

specific to blocks within the MPC8540, and although some of their functionality is described in

Section 4.4.4, “Clocking,” they are defined in detail in their respective chapters.

Note that there is also a CLK_OUT signal in the MPC8540; the signal driven on the CLK_OUT

pin is selectable and described in Section 18.4.1.16, “Clock Out Control Register (CLKOCR).”

4.3

Memory Map/Register Definition

This section describes the configuration and control registers that control access to the

configuration space and to the boot code as well as guidelines for accessing these regions. It also

contains a brief description of the boot sequencer which may be used to initialize configuration

registers or memory before the CPU is released to boot.

4.3.1

Local Configuration Control

Table 4-4 shows the memory map for the configuration, control, and status registers.

Table 4-3. Clock Signals—Detailed Signal Descriptions

Signal

Description

SYSCL

System clock/PCI clock (SYSCLK/PCI_CLK). SYSCLK is the primary clock input to the MPC8540. It is

the clock source for the e500 core and for all devices and interfaces that operate synchronously with the

core. Multiplied up with a phased-lock loop (PLL) to create the core complex bus (CCB) clock (also called

the platform clock) which is used by virtually all of the synchronous system logic, include the L2 cache,

the DDR SDRAM and local bus memory controllers, and other internal blocks such as the DMA and

interrupt controllers. The CCB clock, in turn, feeds the PLL in the e500 core and the DLLs that create the

DDR SDRAM and local bus memory clocks.

When the PCI/PCI-X interface is used, SYSCLK also functions as the PCI_CLK signal. Note that this is

true whether the MPC8540 is in agent or host mode. The MPC8540 does not provide a separate

PCI_CLK output in host mode.

Timing Assertion/Negation—See the MPC8540 Integrated Processor Hardware Specifications for

specific timing information for this signal.

RTC

Real time clock. May be used (optionally) to clock the time base of the e500 core. The maximum input

frequency should not exceed 1/8th the core frequency. See Section 4.4.4.4, “Real Time Clock.” This

signal can also be used (optionally) to clock the global timers in the programmable interrupt controller

(PIC).

Timing Assertion/Negation—See the MPC8540 Integrated Processor Hardware Specifications for

specific timing information for this signal.

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