MPC8540 datasheet(207/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

4-21

PORDBGMSR (POR debug mode register) described in Section 18.4.1.5, “POR Debug Mode

Status Register (PORDBGMSR).”

4.4.3.18 DDR Debug Configuration

The DDR debug configuration input, shown in Table 4-26, enables a DDR memory controller

debug mode in which the DDR SDRAM source ID field and data valid strobe are driven onto the

ECC pins. ECC checking and generation are disabled in this case. ECC signals driven from the

SDRAMs must be electrically disconnected from the ECC I/O pins of the MPC8540 in this mode.

Note that the value latched on this signal during POR is accessible through the memory-mapped

PORDBGMSR (POR debug mode register) described in Section 18.4.1.5, “POR Debug Mode

Status Register (PORDBGMSR).”

4.4.3.19 PCI/PCI-X Output Hold Configuration

The PCI output hold configuration inputs configure the output hold times for the PCI or PCI-X

output drivers. The meanings are different for PCI and PCI-X because the required hold times are

different in the two specifications. In either mode, the default value will meet the hold times

required by the respective specification. Hold times are adjusted by adding or subtracting buffer

delays to the intrinsic delay of the output driver. Refer to the MPC8540 Integrated Processor

Hardware Specifications for specific timing information. Table 4-27 shows the hold time

configurations for PCI mode, and Table 4-28 shows the hold time configurations for PCI-X mode.

Table 4-25. Memory Debug Configuration

Functional

Signal

Reset Configuration

Name

Value

(Binary)

Meaning

MSRCID0

Default (1)

cfg_mem_debug

Debug information from the local bus controller (LBC) is driven on the

MSRCID and MDVAL signals.

Debug information from the DDR SDRAM controller is driven on the

MSRCID and MDVAL signals (default).

Table 4-26. DDR Debug Configuration

Functional

Signal

Reset Configuration

Name

Value

(Binary)

Meaning

MSRCID1

Default (1)

cfg_ddr_debug

Debug information is driven on the ECC pins instead of normal ECC

I/O. ECC signals from memory devices must be disconnected.

Debug information is not driven on ECC pins. ECC pins function in their

normal mode (default).

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