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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8540 датащи(PDF) 175 Page - Freescale Semiconductor, Inc |
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MPC8540 датащи(HTML) 175 Page - Freescale Semiconductor, Inc |
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175 / 1302 page  Signals Overview MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 3-7 FEC_TX_CLK FEC transmit clock in 10/100 — 1 I 21-1/21-8 FEC_CRS FEC carrier sense 10/100 — 1 I 21-1/21-8 FEC_COL FEC collision detect 10/100 — 1 I 21-1/21-8 FEC_RXD[0:3] FEC receive data 10/100 — 4 I 21-1/21-8 FEC_RX_DV FEC receive data valid 10/100 — 1 I 21-1/21-8 FEC_RX_ER FEC receiver error 10/100 — 1 I 21-1/21-8 FEC_RX_CLK FEC receive clock 10/100 — 1 I 21-1/21-8 LAD[0:31] LBC address/data LBC cfg_gpporcr 32 I/O 13-1/13-5 LDP[0:3] LBC data parity LBC — 4 I/O 13-1/13-5 LA27 LBC burst address LBC cfg_cpu_boot 1 O 13-1/13-5 LA[28:31] LBC port address LBC cfg_sys_pll0 cfg_sys_pll1 cfg_sys_pll2 cfg_sys_pll3 4O 13-1/13-5 LCS[0:4] LBC chip select 0–4 LBC — 5 O 13-1/13-5 LCS5 LBC chip select 5 LBC DMA_DREQ2 1O 13-1/13-5 LCS6 LBC chip select 6 LBC DMA_DACK2 1O 13-1/13-5 LCS7 LBC chip select 7 LBC DMA_DDONE2 1O 13-1/13-5 LWE[0:1]/ LSDDQM[0:1]/ LBS[0:1] LBC write enable/byte lane data mask/byte select 0–1 LBC cfg_pci_hold[0:1] 2 O 13-1/13-5 LWE[2:3]/ LSDDQM[2:3]/ LBS[2:3] LBC write enable/byte lane data mask/byte select 2–3 LBC cfg_host_agt0 cfg_host_agt1 2O 13-1/13-5 LBCTL LBC data buffer control LBC — 1 O 13-1/13-5 LALE LBC address latch enable LBC cfg_core_pll0 1 O 13-1/13-5 LGPL0/LSDA10 LBC UPM general purpose line 0/SDRAM address bit 10 LBC cfg_rio_clk0 1 O 13-1/13-5 LGPL1/LSDWE LBC GP line 1/SDRAM write enable LBC cfg_rio_clk1 1 O 13-1/13-5 LGPL2/LOE/ LSDRAS LBC GP line 2/output enable/SDRAM RAS LBC cfg_core_pll1 1 O 13-1/13-5 LGPL3/LSDCAS LBC GP line 3/SDRAM CAS LBC cfg_boot_seq0 1 O 13-1/13-5 Table 3-1. MPC8540 Signal Reference by Functional Block (continued) Name Description Functional Block Alternate Function(s) No. of Signals I/O Table/ Page |
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