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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8540 датащи(PDF) 171 Page - Freescale Semiconductor, Inc |
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MPC8540 датащи(HTML) 171 Page - Freescale Semiconductor, Inc |
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171 / 1302 page  Signals Overview MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 3-3 Figure 3-1. MPC8540 Signal Groupings MPC8540 1 MDQ[0:63] MECC[0:7] MDM[0:7] MDQS[0:7] MDM[8] MDQS[8] MBA[0:1] MA[0:14] 64 8 8 1 8 1 2 15 MWE MRAS MCAS MCS[0:3] 1 1 1 4 MCKE[0:1] 2 RIO_RCLK, RIO_RCLK RIO_RD[0:7], RIO_RD[0:7] 2 16 RIO_RFRAME, RIO_RFRAME RIO_TCLK, RIO_TCLK 2 2 RIO_TD[0:7], RIO_TD[0:7] RIO_TFRAME, RIO_TFRAME 16 2 PCI_REQ0 PCI_REQ[4:1] PCI_GNT0 PCI_GNT[4:1] EC_MDC EC_MDIO 1 4 1 4 1 1 TSEC1_TX_EN TSEC1_TX_ER TSEC1_TX_CLK 8 1 1 1 TSEC1_GTX_CLK TSEC1_CRS 1 1 TSEC1_COL TSEC1_RXD[7:0] 1 8 TSEC1_RX_DV TSEC1_RX_ER 1 1 TSEC1_RX_CLK 1 32 4 1 4 4 4 4 1 Local Bus Interface 1 1 1 1 1 1 1 1 9 3 1 1 1 Power Management 1 1 1 1 1 1 1 5 1 1 1 1 67 Signals 1 Signal PCI_AD[63:0] 64 PCI_C/BE[7:0] PCI_PAR, PCI_PAR64 PCI_FRAME PCI_TRDY 8 2 1 1 PCI_IRDY PCI_STOP 1 1 PCI_DEVSEL PCI_IDSEL 1 1 PCI_REQ64 PCI_ACK64 1 1 PCI_PERR PCI_SERR 1 1 Test 6 Signals 8 1 1 1 1 1 1 8 1 1 1 LWE[0:3]/LSDDQM[0:3]/LBS[0:3] LBCTL LALE LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LOE/LSDRAS LGPL3/LSDCAS LGPL4/LGTA/LUPWAIT/LPBSE LGPL5 LAD[0:31] LDP[0:3] LA27 LA[28:31] LCS[0:3] LCS[4:7] ASLEEP LSSD_MODE L1_TSTCLK L2_TSTCLK MCP UDE IRQ[0:8] IRQ[9:11] IRQ_OUT IIC_SDA IIC_SCL HRESET HRESET_REQ SRESET CKSTP_IN CKSTP_OUT TRIG_IN TRIG_OUT MSRCID[0:4] MDVAL TSEC1_TXD[7:0] EC_GTX_CLK125 1 1 PIC Interface 15 Signals System Control 6 Signals Debug 8 Signals PCI/PCI-X Interface 94 Signals DMA_DREQ[0:1],DMA_DREQ[2:3] DMA_DACK[0:1],DMA_DACK[2:3] DMA_DDONE[0:1],DMA_DDONE[2:3] 4 4 4 I2C Interface 2 Signals Ethernet Interface 3 Signals TSEC1 Ethernet Interface 25 Signals DMA Interface 12 Signals TSEC2 Ethernet Interface 25 Signals TSEC2_TX_EN TSEC2_TX_ER TSEC2_TX_CLK TSEC2_GTX_CLK TSEC2_CRS TSEC2_COL TSEC2_RXD[7:0] TSEC2_RX_DV TSEC2_RX_ER TSEC2_RX_CLK TSEC2_TXD[7:0] RapidIO Interface 42 Signals Memory Interface 130 Signals MCK[0:5], MCK[0:5] 12 MSYNC_IN, MSYNC_OUT 2 RIO_TX_CLK_IN, RIO_TX_CLK_IN 2 1 LCKE 3 LCLK[0:2] 2 LSYNC_IN, LSYNC_OUT Clock 1 1 3 Signals SYSCLK RTC 1 TEST_SEL 1 1 JTAG 5 Signals 1 1 1 TCK TDI TDO TMS TRST 2 2 2 UART_SIN[0:1] UART_SOUT[0:1] UART_CTS[0:1] UART_RTS[0:1] 2 Dual UART Interface 8 Signals 4 1 1 1 1 1 4 1 1 1 10/100 Ethernet Interface 16 Signals FEC_TX_EN FEC_TX_ER FEC_TX_CLK FEC_CRS FEC_COL FEC_RXD[3:0] FEC_RX_DV FEC_RX_ER FEC_RX_CLK FEC_TXD[3:0] 1 CLK_OUT 1 READY 2 THERM[0:1] |
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