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MPC8540 датащи(PDF) 155 Page - Freescale Semiconductor, Inc |
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MPC8540 датащи(HTML) 155 Page - Freescale Semiconductor, Inc |
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155 / 1302 page ![]() Complete CCSR Map MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 2-37 0x4_1200– 0x4_12F0 Reserved — — — 0x4_1300 TCR—Timer control register R/W 0x0000_0000 10.3.2.6/10-24 0x4_1310 IRQSR0—IRQ_OUT summary register 0 R 0x0000_0000 10.3.3.1/10-26 0x4_1320 IRQSR1—IRQ_OUT summary register 1 R 0x0000_0000 10.3.3.2/10-27 0x4_1330 CISR0—Critical Interrupt summary register 0 R 0x0000_0000 10.3.3.3/10-27 0x4_1340 CISR1—Critical Interrupt summary register 1 R 0x0000_0000 10.3.3.4/10-28 0x4_1350 PM0MR0—Performance monitor 0 mask register 0 R/W 0x00FF_FFFF 10.3.4.1/10-29 0x4_1360 PM0MR1—Performance monitor 0 mask register 1 R/W 0xFFFF_FFFF 10.3.4.2/10-30 0x4_1370 PM1MR0—Performance monitor 1 mask register 0 R/W 0x00FF_FFFF 10.3.4.1/10-29 0x4_1380 PM1MR1—Performance monitor 1 mask register 1 R/W 0xFFFF_FFFF 10.3.4.2/10-30 0x4_1390 PM2MR0—Performance monitor 2 mask register 0 R/W 0x00FF_FFFF 10.3.4.1/10-29 0x4_13A0 PM2MR1—Performance monitor 2 mask register 1 R/W 0xFFFF_FFFF 10.3.4.2/10-30 0x4_13B0 PM3MR0—Performance monitor 3 mask register 0 R/W 0x00FF_FFFF 10.3.4.1/10-29 0x4_13C0 PM3MR1—Performance monitor 3 mask register 1 R/W 0xFFFF_FFFF 10.3.4.2/10-30 0x4_13D0– 0x4_13F0 Reserved — — — 0x4_1400 MSGR0—Message register 0 R/W 0x0000_0000 10.3.5.1/10-30 0x4_1410 MSGR1—Message register 1 0x4_1420 MSGR2—Message register 2 0x4_1430 MSGR3—Message register 3 0x4_1440– 0x4_14F0 Reserved — — — 0x4_1500 MER—Message enable register R/W 0x0000_0000 10.3.5.2/10-31 0x4_1510 MSR—Message status register R/W 0x0000_0000 10.3.5.3/10-31 0x4_1520– 0x4_FFF0 Reserved — — — PIC Register Address Map—Interrupt Source Configuration Registers 0x5_0000 EIVPR0—External interrupt 0 (IRQ0) vector/priority register R/W 0x8000_0000 10.3.6.1/10-32 0x5_0010 EIDR0—External interrupt 0 (IRQ0) destination register R/W 0x0000_0001 10.3.6.2/10-33 0x5_0020 EIVPR1—External interrupt 1 (IRQ1) vector/priority register R/W 0x8000_0000 10.3.6.1/10-32 0x5_0030 EIDR1—External interrupt 1 (IRQ1) destination register R/W 0x0000_0001 10.3.6.2/10-33 0x5_0040 EIVPR2—External interrupt 2 (IRQ2) vector/priority register R/W 0x8000_0000 10.3.6.1/10-32 Table 2-9. Memory Map (continued) Offset Register Access Reset Section/Page |
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