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MPC8540 датащи(PDF) 295 Page - Freescale Semiconductor, Inc

номер детали MPC8540
подробное описание детали  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 датащи(HTML) 295 Page - Freescale Semiconductor, Inc

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Debug Registers
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
6-45
6.13.1.3 Debug Control Register 2 (DBCR2)
32
33
34
35
36
37
38
39
40
41
42
63
Field DAC1US DAC1ER DAC2US DAC2ER DAC12M
—
Reset
All zeros
R/W
R/W
SPR
SPR 310
Figure 6-50. Debug Control Register 2 (DBCR2)
Table 6-34. DBCR2 Field Descriptions
Bits
Name
Description
32–33
DAC1US Data address compare 1 user/supervisor mode
00 DAC1 debug events can occur
01 Reserved
10 DAC1 debug events can occur only if MSR[PR] = 0.
11 DAC1 debug events can occur only if MSR[PR] = 1.
34–35
DAC1ER Data address compare 1 effective/real mode
00 DAC1 debug events are based on effective addresses.
01 Reserved on the e500
10 DAC1 debug events are based on effective addresses and can occur only if MSR[DS] = 0.
11 DAC1 debug events are based on effective addresses and can occur only if MSR[DS] = 1.
36–37
DAC2US Data address compare 2 user/supervisor mode
00 DAC2 debug events can occur.
01 Reserved
10 DAC2 debug events can occur only if MSR[PR] = 0.
11 DAC2 debug events can occur only if MSR[PR] = 1.
38–39
DAC2ER Data address compare 2 effective/real mode
00 DAC2 debug events are based on effective addresses.
01 Reserved on the e500
10 DAC2 debug events are based on effective addresses and can occur only if MSR[DS] = 0.
11 DAC2 debug events are based on effective addresses and can occur only if MSR[DS] = 1.



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