CP3SP33SMSSLASHNOPB datasheet(103/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

17 Multi-Input Wake-Up

The Multi-Input Wake-Up (MIWU) module allows most general-purpose I/O port pins, certain peripheral

pins (that do not share functionality with a GPIO port), and certain peripheral events to break the system

out of a low-power mode and return to Active mode. Each MIWU input can be programmed to assert a

wake-up signal for exiting from a low-power mode, and each input can be independently programmed to

assert an interrupt request on any of eight maskable interrupts assigned to the MIWU module.

Eight types of registers control the generation of interrupts and wake-up events, and one register indicates

the status of pending interrupt requests:

•

WKRPNDx—two 32-bit registers indicate which MIWU inputs have detected rising edges since they

were last cleared (either by reset or writing to WKCLRx).

•

WKFPNDx—two 32-bit registers indicate which MIWU inputs have detected falling edges since they

were last cleared (either by reset or writing to WKCLRx).

•

WKCLRx—writing 1 to bits in either of these two 32-bit registers clears the corresponding bits in the

WKRPNDx and WKFPNDx registers. The WKCLRx registers are write-only.

•

WKRENx—two 32-bit registers hold bits for enabling a wake-up event when a rising edge is detected

on the corresponding MIWU input.

•

WKFENx—two 32-bit registers hold bits for enabling a wake-up event when a falling edge is detected

on the corresponding MIWU input.

•

WKREINx—two 32-bit registers hold bits for enabling an interrupt when a rising edge is detected on

the corresponding MIWU input.

•

WKFEINx—two 32-bit registers hold bits for enabling an interrupt when a falling edge is detected on

the corresponding MIWU input.

•

WKICTLx—four 32-bit registers provide two-bit fields to select one of four MIWU interrupt channels

available when an enabled interrupt occurs. MIWU inputs 31:0 can only assert MIWU interrupts 3:0,

while MIWU inputs 63:32 can only assert MIWU interrupts 7:4.

•

WKISTAT—indicates pending MIWU interrupts.

The MIWU module is always active, including in Halt mode when all device clocks are stopped. Therefore,

detecting an external trigger condition and setting bits in WKRPNDx and WKFPNDx do not require an

active HCLK Clock or PCLK Clock.

Multi-Input Wake-Up

103

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