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CP3SP33SMS/NOPB датащи(PDF) 52 Page - Texas Instruments |
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CP3SP33SMS/NOPB датащи(HTML) 52 Page - Texas Instruments |
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52 / 407 page ![]() CP3SP33 SNOSCW5 – MAY 2013 www.ti.com 10.5 Usage Notes The EBIU registers must be programmed in the following sequence: 1. SCSLRn 2. SMSKRn 3. SMTMGR_SETn 4. FLASH_TRPDR 5. SMCTRL 11 System Configuration 11.1 Operating Environment The operating environment controls the reset vector (boot address). In ERE16 mode, the vector is 0040 0000h. In ERE32 mode, the vector is 0080 0000h. The operating mode of the device is controlled by the states sampled from the ENV[1:0] pins at reset, as shown in Table 11-1. Internal pullups on the ENV[1:0] pins select ERE16 mode if these pins are allowed to float. Table 11-1. Operating Environment Selection ENV[1:0] OPERATING ENVIRONMENT 11 ERE16 mode (boot from 0040 0000h) 10 ERE32 mode (boot from 0080 0000h) 11.2 Freeze Mode For debugging purposes, a Freeze mode is available which has the following effects: • Disables maskable interrupts. • Suspends DMA transactions. • Inhibits certain state changes in the following modules (see individual module descriptions for details): Advanced Audio Interface, A/D Converter, Codec, CVSD/ PCM Converters, Multi-Function Timers, Timing and Watchdog Module, and Versatile Timer Units. • Inhibits automatic clear-on-read function applied to the register bits listed in Table 11-2. Table 11-2. Register Bits Affected By Freeze Mode MODULE REGISTERS BITS ACCESS.bus ACBnST SDAST ADC_DONE, ADC_OFLW, A/D Converter ADCRESLT SIGN, ADC_RESULT ARSCR RXO, RXE, RXF, RXAF Advanced Audio Interface (AAI) ATSCR TXU, TXF, TXE, TXAE Codec TCDCADCn ADCDATA CVSD/PCM Converter CVSTATn PCMINT, CVE, CVF Microwire/SPI MWnDAT RBF Timing and Watchdog Module T0CSR TC URBUFn URBF USART0, UART 1, 2, 3 USTATn UPE, UFE, UDOE, UBKD 52 System Configuration Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :CP3SP33 |
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