CP3SP33SMSSLASHNOPB datasheet(57/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

Table 12-1. DMA-Capable Peripherals (continued)

SRCRQ

PERIPHERAL

TRANSACTION

ASC CHANNEL

MWSPI0

MWDAT

MWSPI0

MWDAT

ACCESS.bus 0

R/W

ACBSDA

The DMA request and DMA acknowledge signals for peripherals shared with the DSP DMA controller are

sent through the Audio Subsystem Controller (ASC), which multiplexes these signals between the CPU

DMA controller and the DSP DMA controller. In Table 12-1, the ASC channel number refers to the

multiplexer channel used to select the DMA controller that handles the DMA request and acknowledge

signals for that peripheral.

12.2 Transfer Types

The DMAC supports three transfer types:

•

Single Transfers—A single read cycle followed by a single write cycle.

•

Burst Transfers—A four-cycle burst read from memory followed by a four-cycle burst write to memory.

Software DMA requests (memory-to-memory block transfers) are always burst transfers.

•

Data Collection Transfers—A four-cycle burst read from memory followed by four single-cycle writes to

a peripheral, or four single-cycle reads from a peripheral followed by a four-cycle burst write to

memory.

Priority among DMA requests is linear for transfers of the same type (channel 0 has highest priority),

however burst transfers and data collection transfers have priority over single transfers.

During a single transfer, the transfer cycle size (number of bytes per cycle) is controlled by the WMODE

and TCS bits of the DMACNTn register, as shown in Table 12-2. During a burst, the transfer cycle size is

always 4 bytes.

Table 12-2. Transfer Cycle Size

TRANSFER CYCLE SIZE

WMODE

TCS

1 Byte

2 Bytes

4 Bytes

The transfer type is selected by the SWRQ and BBE bits in the DMACNTn register, as shown in

Table 12-3. Only channels 0 and 1 support data collection mode.

Table 12-3. DMA Transfer Types

TRANSFER TYPE

SWRQ

BBE

Single Cycle

Data Collection

Burst

CPU DMA Controller

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