CP3SP33SMSSLASHNOPB datasheet(67/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

12.9.10 DMA Status Register n (DMASTATn)

The DMA status register is a 32-bit register that holds the status information for the DMA channel. This

bits are sticky (once set by the occurrence of the specific condition, they remain set until explicitly cleared

by software). These bits can be cleared by writing 1 to their bit positions in the DMASTAT register to be

cleared. Writing 0 to these bits has no effect.

16 15

8 7

Reserved

BLV

Reserved

BNE

ERR

VLD

CHAC

OVR

The Terminal Count bit indicates whether the transfer was completed by a terminal count

condition (BLTCn Register reached 0 and the PF bit was clear).

0 – Terminal count condition did not occur.

1 – Terminal count condition occurred.

OVR

The behavior of the Channel Overrun bit depends on the operation mode (single buffer,

double buffer, or auto-initialize) of the DMA channel.

In double-buffered mode (DMACNTn.OT = 0): The OVR bit is set when the present transfer

is completed (BLTCn = 0), but the parameters for the next transfer (address and block

length) are not valid (DMASTATn.VLD = 0).

In auto-initialize mode (DMACNTn.OT = 1): The OVR bit is set when the present transfer is

completed (BLTCn = 0), and the DMASTATn.TC bit is still set.

In single-buffer mode: Operates in the same way as double-buffer mode. In single-buffered

mode, the DMASTATn.VLD bit should always be clear, so it will also be set when the

DMASTATn.TC bit is set. Therefore, the OVR bit can be ignored in this mode.

CHAC

The Channel Active bit continuously indicates the active or inactive status of the channel, and

therefore, it is read-only. Data written to the CHAC bit is ignored.

0 – Channel inactive.

1 – Indicates that the channel is active (CHEN bit in the CNTLn register is 1 and BLTCn > 0)

VLD

The Transfer Parameters Valid bit indicates whether the transfer parameters for the next

block to be transferred are valid. Writing the BLTRn register automatically sets this bit. The

bit is cleared in the following cases:

● The present transfer is completed and the ADRAn, ADRBn, and BLTRn registers have

been loaded to the ADCAn, ADCBn, and BLTCn registers.

● Writing 1 to the VLD bit.

ERR

The Error bit indicates whether an error response has been detected during the last transfer.

This may occur because the address was invalid or an incremental access goes out of

bounds.

0 – Error condition did not occur.

1 – Error condition occurred.

BNE

The Buffer Not Empty bit indicates whether there is valid data in the burst buffer.

0 – Burst buffer is empty.

1 – Burst buffer holds valid data.

BLV

The Burst Buffer Level field indicates the number of valid bytes in the burst buffer.

The Timeout bit indicates that a timeout event occurred (RQTCNTn reached its terminal

count). This bit is cleared every time the DMA request for this channel is asserted.

0 – No timeout occurred since this bit was last cleared.

1 – A timeout occurred.

CPU DMA Controller

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