CP3SP33SMSSLASHNOPB datasheet(40/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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RRIE0

The Reply Register 0 Interrupt Enable bit asserts IRQ60 to the CPU interrupt controller on

DSP writes to the APBP_REP0 register.

0 – Interrupt disabled.

1 – Interrupt enabled.

RRIE1

The Reply Register 1 Interrupt Enable bit asserts IRQ60 to the CPU interrupt controller on

DSP writes to the APBP_REP1 register.

0 – Interrupt disabled.

1 – Interrupt enabled.

RRIE2

The Reply Register 2 Interrupt Enable bit asserts IRQ60 to the CPU interrupt controller on

DSP writes to the APBP_REP2 register.

0 – Interrupt disabled.

1 – Interrupt enabled.

MEMSEL

The Memory Select field selects the DSP memory space accessed by the CPU. Values other

than those listed below are reserved. 0000 – DSP data memory.

0001 – MMIO registers.

0101 – DSP program memory.

0110 – Expansion bus (16M EBIU region).

0111 – Expansion bus (240M EBIU region).

9.3.6

CPU/DSP Interface Status Register (PSTS)

The PSTS register is a 16-bit, read-only register that provides status bits for the CPU/DSP interface.

WFFI

RFNEI

RFFI

Reserved

PRST

WTIP

RTIP

RCOMIM2

RCOMIM1

RCOMIM0

RRI2

RRI1

RRI0

PSEMI

WFEI

RTIP

The Read Transfer in Progress bit indicates when a read transfer is in progress. A read

transfer can be terminated while it is in progress by writing 0 to the PCFG.RS bit.

0 – No transfer is in progress.

1 – A transfer is in progress.

WTIP

The Write Transfer In Progress bit indicates when a write transfer is in progress.

0 – No transfer is in progress.

1 – A transfer is in progress.

PRST

The Peripheral Reset Indicator bit is asserted from the start of DSP reset (PCFG.DSPR = 1)

until the reset has completed. When the bit goes clear, the MMIO registers have received

their reset values. The CPU must poll this bit before downloading software to the DSP.

0 – DSP is not in reset.

1 – DSP reset in progress.

RFFI

The Read FIFO Full Indicator bit is asserted when the read FIFO is full.

0 – FIFO is not full.

1 – FIFO is full.

RFNEI

The Read FIFO Not Empty Indicator bit is asserted when the read FIFO holds valid data.

0 – FIFO is empty.

1 – FIFO holds valid data.

WFFI

The Write FIFO Full Indicator bit is asserted when the write FIFO is full.

0 – FIFO is not full.

1 – FIFO is full.

DSP and Audio Peripherals

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