CP3SP33SMSSLASHNOPB datasheet(72/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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Table 13-3. Interrupt Controller Registers

NAME

ADDRESS

DESCRIPTION

IVECT

FF FE00h

Interrupt Vector Register

NMISTAT

FF FE04h

Non-Maskable Interrupt Status Register

EXNMI

FF FE08h

External NMI Trap Control and Status Register

ISTR0

FF FE10h

Interrupt Status Register 0

ISTR1

FF FE14h

Interrupt Status Register 1

ISTR2

FF FE18h

Interrupt Status Register 2

IENR0

FF FE20h

Interrupt Enable and Mask Register 0

IENR1

FF FE24h

Interrupt Enable and Mask Register 1

IENR2

FF FE28h

Interrupt Enable and Mask Register 2

SOFTR0

FF FE40h

Software Interrupt Register 0

SOFTR1

FF FE44h

Software Interrupt Register 1

SOFTR2

FF FE48h

Software Interrupt Register 2

INTGPAR0

FF FE50h

Interrupt Priority Group A Register 0

INTGPAR1

FF FE58h

Interrupt Priority Group A Register 1

INTGPAR2

FF FE60h

Interrupt Priority Group A Register 2

INTGPBR0

FF FE54h

Interrupt Priority Group B Register 0

INTGPBR1

FF FE5Ch

Interrupt Priority Group B Register 1

INTGPBR2

FF FE64h

Interrupt Priority Group B Register 2

IDBG

FF FEFCh

Interrupt Debug Register

13.6.1 Interrupt Vector Register (IVCT)

The IVCT register is a 32-bit, read-only register which reports the encoded value of the highest priority

maskable interrupt that is both asserted and enabled. The register is read by the CPU during an interrupt

acknowledge bus cycle, and INTVECT is valid during that time. It may contain invalid data while INTVECT

is updated. The register is initialized to 0000 0010h at reset.

8M 7

Reserved

INTVECT

The Interrupt Vector field indicates the highest priority interrupt which is both asserted and

enabled. The valid range is from 10h to 56h.

13.6.2 Non-Maskable Interrupt Status Register (NMISTAT)

The NMISTAT register is a 32-bit, read-only register. It holds the status of the current pending Non-

Maskable Interrupt (NMI) requests. On the CP3SP33, the external NMI input is the only source of NMI

interrupts. The NMISTAT register is cleared on reset and each time its contents are read.

Reserved

EXT

The External NMI request bit indicates whether an external non-maskable interrupt request has

occurred. Refer to the description of the EXNMI register below for additional details.

0 – No external NMI request.

1 – External NMI request has occurred.

13.6.3 External NMI Trap Control and Status Register (EXNMI)

The EXNMI register is a 32-bit, read/write register. It indicates the current value of the NMI pin and

controls the NMI interrupt trap generation based on a falling edge of the NMI pin. ENCLK, PIN, and EN

are cleared on reset. When writing to this register, all reserved bits must be written with 0 for the device to

function properly

Interrupts

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