CP3SP33SMSSLASHNOPB datasheet(29/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

On an instruction fetch, address bits 9:4 select one of the lines. Any of the four ways may hold the target

of the instruction fetch. The tags in each of the four ways are compared against bits 32:10 of the

instruction address to determine which way (if any) holds the data. If one of the entries has matching

address bits and its valid bit is set, the instruction fetch is a cache hit, and the cache data is passed to the

CPU to satisfy the instruction fetch.

If none of the valid tags match the instruction address bits, the instruction fetch is a cache miss, and a bus

cycle will be generated on the CPU core bus to read the memory location containing the target of the

instruction fetch. When the memory data is received, it is loaded into the cache and passed to the CPU,

which releases the CPU to continue execution. Three subsequent bus cycles read the remainder of an

aligned 16-byte block to fill a cache entry.

A PLRU algorithm is used to allocate a cache entry in one of the four ways to receive the block. For each

line, there are three bits B2:0 used by the algorithm. These bits are not directly visible to application

software, but they may be indirectly visible by their effect on the execution speed of some programs. (It

would be unusual for execution speed to be significantly affected.)

The way selected by the PLRU bits is shown in Table 7-1.

Table 7-1. Way Selected for Allocation on Cache Miss

B2:0

Way Selected for Allocation

Way 0

Way 2

Way 1

Way 2

100

Way 0

101

Way 3

110

Way 1

111

Way 3

The PLRU bits are cleared when the cache is disabled, and they are updated on a cache hit. Table 7-2

shows the next state of the PLRU bits when they are updated.

Table 7-2. Next State of PLRU Bits on Cache Hit

Way Selected by Cache Hit

Way 0

Unchanged

Way 1

Unchanged

Way 2

Unchanged

Way 3

Unchanged

7.1

Cache Locking

Cache locking is typically used for performance-sensitive algorithms, to assure that the program memory

will be in the cache during execution. It may also be used when deterministic behavior is required, to

ensure that programs always execute in the same number of cycles.

When the cache is locked, the contents of the cache do not change. The cache is locked by setting the

LIC bit in the CFG register.

When a cache miss occurs while the cache is locked, no cache entry is allocated on a cache miss, and

the PLRU bits are not updated.

Instruction Cache

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