CP3SP33SMSSLASHNOPB datasheet(75/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

SOFT0

The Software Interrupt bits activate the corresponding maskable interrupt when written with 1.

0 – Interrupt is not active.

1 – Interrupt is active.

13.6.11 Software Interrupt Register 1 (SOFTR1)

The SOFTR1 register is a 32-bit, read/write register. Setting a bit in this register activates the

corresponding maskable interrupt IRQ63 to IRQ31. The register is initialized to 0000 0000h at reset.

SOFT1

The Software Interrupt bits activate the corresponding maskable interrupt when written with 1.

0 – Interrupt is not active.

1 – Interrupt is active.

13.6.12 Software Interrupt Register 2 (SOFTR2)

The SOFTR2 register is a 32-bit, read/write register. Setting a bit in this register activates the

corresponding maskable interrupt IRQ70 to IRQ64. Only bits 6:0 of this register are used. The register is

initialized to 0000 0000h at reset.

SOFT2

The Software Interrupt bits activate the corresponding maskable interrupt when written with 1.

0 – Interrupt is not active.

1 – Interrupt is active.

13.6.13 Interrupt Priority Group A Register 0 (INTGPAR0)

The INTGPAR0 register is a 32-bit, read/write register. Bits in this register specify the least significant bit

for selecting the priority group of the corresponding interrupt IRQ31 to IRQ1. Bit 0 of this register is

reserved. The register is initialized to 0000 0000h at reset.

INTGPA0

Reserved

INTGPA0

The Interrupt Priority Group A bits specify the least significant bit for selecting one of four

interrupt priority groups.

0 – Interrupt belongs to group 0 or 2.

1 – Interrupt belongs to group 1 or 3.

13.6.14 Interrupt Priority Group A Register 1 (INTGPAR1)

The INTGPAR1 register is a 32-bit, read/write register. Bits in this register specify the least significant bit

for selecting the priority group of the corresponding interrupt IRQ63 to IRQ31. The register is initialized to

0000 0000h at reset.

INTGPA1

Interrupts

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