CP3SP33SMSSLASHNOPB datasheet(96/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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16 Power Management Module

The Power Management Module (PMM) improves the efficiency of the CP3SP33 by changing the

operating mode (and therefore the power consumption) according to the required level of device activity.

The device implements four power modes:

•

Active Mode—CPU and core bus peripherals operate from HCLK Clock, which is generated by a

prescaler from Main Clock, PLL1 Clock, or PLL2 Clock. Either PLL may be powered down if its output

is not used to gene ate HCLK Clock or any Auxiliary Clock.

•

Power-Save Mode—CPU and core bus peripherals operate from Slow Clock. Any of the PLLs and

high-frequency oscillator may be powered down, if its output is not used to generate Slow Clock or any

Auxiliary Clock.

•

Idle Mode—CPU and most or all peripherals are powered down. A watchdog timeout (from a timer

running on Slow Clock), external reset, or MIWU input can break out of this mode.

•

Halt Mode—only an external reset or MIWU input can break out of this mode.

Table 16-1 summarizes the differences between power modes: the state of the high-frequency oscillator

(on or off), PLLs, HCLK Clock source (clock used by CPU and core bus peripherals), and clock source

used by the Timing and Watchdog Module (TWM).

Table 16-1. Power Mode Operating Summary

MODE

HIGH-FREQUENCY OSCILLATOR

PLLs

HCLK CLOCK SOURCE

TWM CLOCK SOURCE

Active

On or Off

Prescaler

Slow Clock

Power Save

On or Off

Slow Clock

Idle

On or Off

None

Slow Clock

Halt

Off

None

The low-frequency oscillator continues to operate in all four modes and power must be provided

continuously to the device power supply pins. In Halt mode, however, Slow Clock does not toggle, and as

a result, the Timing and Watchdog Module does not operate. For the Power Save and Idle modes, the

high-frequency oscillator can be turned on or off under software control, if the low-frequency oscillator is

used to drive Slow Clock.

Software can configure either PLL to be powered down in Active, Power Save, and Idle mode, as long as

it is not driving HCLK Clock or an Auxiliary Clock generator.

Table 16-2 shows the clock sources used by the CP3SP33 device modules and their behavior in each

power mode.

Table 16-2. Module Activity Summary

POWER MODE

MODULE

CLOCK SOURCE(s)

ACTIVE

POWER SAVE

IDLE

HALT

CPU

On/Off

Off

HCLK Clock

MIWU

Active

PCLK Clock

PMM

Active

Slow Clock

TWM

Off

Slow Clock

Bluetooth

On/Off

Off

Aux Clk 1

A/D Converter

On/Off

Off(1)

Aux Clk 1, PCLK Clock

CVSD/PCM 0

On/Off

Off

Aux Clk 2

CVSD/PCM 1

On/Off

Off

Aux Clk 3

Codec

On/Off

Off

Aux Clk 1, Aux Clk 4, PCLK Clock, PLL1 Clk, PLL2

Clk, I2SCLK, AAI SCK, TCIO1

(1)

The Analog/Digital Converter (ADC) module is not automatically disabled by entering Halt mode, however its clock is stopped so no

conversions may be performed in Halt mode. For maximum power savings, software must disable the ADC module before entering Halt

mode.

Power Management Module

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