CP3SP33SMSSLASHNOPB datasheet(39/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

9.3.4

DSP DMA Channel 0 Address Register (PADR)

The PADR register is a 16-bit, write-only register that provides the lower 16 address bits for DSP DMA

Channel 0. The page address (page 0) must be programmed in the DSP DMA controller. In autoincrement

mode (PCFG.AIM = 1), this address is autoincremented on every DMA cycle. After reset, this register is

clear.

PADR

9.3.5

CPU/DSP Interface Configuration Register (PCFG)

The PADR register is a 16-bit, read/write register that controls the configuration of the CPU/DSP interface.

After reset, this register is clear.

MEMSEL

RRIE2 RRIE1

RRIE0

WFEIE

WFFIE

RFNEIE

RFFIE

DRS

AIM

DSPR

The DSP Reset bit, when set, resets the DSP. To properly reset the DSP, this bit must

remain set for 8 DSP clock cycles.

0 – DSP reset is not asserted.

1 – DSP reset is asserted.

AIM

The Autoincrement Mode bit enables automatic increment of the address counter when the

CPU uses DSP DMA channel 0 (the host interface used for downloading to the DSP).

0 – No increment of the DMA address.

1 – Automatic increment enabled.

DRS

The Data Read Select field selects the transfer mode used on the 32-bit high-performance

DSP bus to read data for satisfying a CPU read request. This field is ignored if the RS bit is

clear.

00 – Single read transfer.

01 – 8-word burst read transfer.

10 – 16-word burst read transfer.

11 – Free running (continuous).

Setting the Read Start bit initiates a read transfer of the type specified in the DRS field.

Clearing the bit flushes the read FIFO and terminates any read transfer in progress.

0 – No transfer is initiated or in progress.

1 – Write 1 to initiate a read transfer.

RFFIE

The Read FIFO Full Interrupt Enable bit asserts IRQ60 to the CPU interrupt controller when

the read FIFO becomes full.

0 – Interrupt disabled.

1 – Interrupt enabled

RFNEIE

The Read FIFO Not Empty Interrupt Enable bit asserts IRQ60 to the CPU interrupt controller

when the read FIFO holds valid data.

0 – Interrupt disabled.

1 – Interrupt enabled.

WFFIE

The Write FIFO Full Interrupt Enable bit asserts IRQ60 to the CPU interrupt controller when

the write FIFO is full.

0 – Interrupt disabled.

1 – Interrupt enabled.

WFEIE

The Write FIFO Empty Interrupt Enable bit asserts IRQ60 to the CPU interrupt controller

when the write FIFO is empty.

0 – Interrupt disabled.

1 – Interrupt enabled.

DSP and Audio Peripherals

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