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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CP3SP33SMS/NOPB датащи(PDF) 48 Page - Texas Instruments |
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CP3SP33SMS/NOPB датащи(HTML) 48 Page - Texas Instruments |
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48 / 407 page  XBEn System Clock DS429 XAn XWE XDn (in) Address A tBTA Data B XOE tBTA XDn (out) Data A XCSn Address B CP3SP33 SNOSCW5 – MAY 2013 www.ti.com Figure 10-4. Bus Turnaround Timing 10.4 EBIU Registers For all registers, the contents should only be changed once, in the initialization routine after reset. The EBIU has two global control registers, two registers specific to each chip select, and 3 registers for defining 3 sets of timing parameters. Any of the chip selects may use any of the timing parameters. Table 10-3. Bus Control Registers NAME ADDRESS DESCRIPTION SMCTLR FF 00A4h Static Memory Control Register SCSLR0 FF 0014h Chip Select Register 0 SMSKR0 FF 0054h Mask Register 0 SCSLR1 FF 0018h Chip Select Register 1 SMSKR1 FF 0058h Mask Register 1 SCSLR2 FF 001Ch Chip Select Register 2 SMSKR2 FF 005Ch Mask Register 2 SMTMGR_SET0 FF 0094h Static Memory Timing Register 0 SMTMGR_SET1 FF 0098h Static Memory Timing Register 1 SMTMGR_SET2 FF 009Ch Static Memory Timing Register 2 FLASH_TRPDR FF 00A0h Flash tRPD Timing Register 48 External Bus Interface Unit Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :CP3SP33 |
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