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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CP3SP33SMS/NOPB датащи(PDF) 13 Page - Texas Instruments |
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CP3SP33SMS/NOPB датащи(HTML) 13 Page - Texas Instruments |
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13 / 407 page  DS408 X2CKI X2CKO 32.768 kHz Crystal VCC RESET X1CKI X1CKO IOVCC XD[31:0] PE0/RXD0/TIO0_1 PE1/TXD0 PE4/CKX0/TIO0_2 ENV1/TSTCLK1 CP3SP33MS (FBGA-224) 12 MHz Crystal or External Clock Input PE5/TA0/NMI ENV0/TSTCLK0 PE8/MSK0 PE9/MDIDO0 PE10/MDODI0 PE11/MWCS0/TIO0_7 PH3/CAN0TX/TIO1_8 PE2/RTS0/TIO0_3 PE3/CTS0 D- D+ TMS TDI TDO TCK RDY XCS0 XCS1 XOE XCS2 XWE XBE[3:0] CPU JTAG Interface GND Operating Environment UVCC UGND PLLVCC PLLGND XA[22:0] USART0/ VTU0 Microwire/Plus SPI 0 NMI ADC ADC[9:0] VREF PE6/CAN1RX PE7/CAN1TX PF7/ASYNC/TB0 PH2/CAN0RX/TIO1_7 PE13/IDPULLUP/TIO1_1 PE14/DRVVBUS/TIO1_3 IOGND ADVCC ADGND MCKO MSEO NEXUS Auxilliary Port and Teak DSP JTAG Interface SCL1 SDA1 TCADCVCC TCADCGND TCDACVCC TCDACGND TCVCM1 TCMIC1P,TCMIC1N TCMIC2P,TCMIC2N TCLP,TCLN TCRP,TCRN TCVCM2 TCVBUF1 TCVBUF2 TCVRFP TCVRFN DSPTMS/MDO0 DSPTDI/MDO1 DSPTDO/MDO2 DSPTCK/MDO3 VBUS PG4/MSK1 PG5/MDIDO1 PG6/MDODI1 PG7/MWCS1/TA1 PG14/RXD3/TB1 PG15/TXD3 PG10/SFS/TCIO1 PG11/STD/DIGMIC2 PG12/SRD PG13/SRCLK/CTS3 Microwire /Plus SPI 1 UART3 AAI PG8/SRFS/RTS3 PG9/SCK/DIGMIC1 PE15/IDDIG/TIO1_5 RFVCC RFGND CLKIN/RFCK External Bus Interface USB Codec RF Interface CAN0 CAN1 ACCESS.bus 1 Power Supply / 4 / 10 / 4 / 12 / 12 / 32 / 23 / 4 Reset PF12/RXD2/TIO0_8 PF13/TXD2 PF14/RTS2/TIO1_2 PF15/CTS2 UART2 PH1/SDA0/TIO1_6 PE12/SCL0/TIO0_5 ACCESS .bus 0 PG0/I2SCLK PG1/I2SWS PG2/I2SSDI PG3/I2SSDO I2 S PH0/TIO1_4 VTU1 PH[15:4] WUI / 12 / 2 / 2 / 2 / 2 PF1/SCLK RFDATA PF0/RFSYNC RFCE PF3/SLE PF4/BTSEQ1 PF2/SDAT PF5/BTSEQ2 PF6/BTSEQ3 PF8/RXD1/TIO0_4 PF9/TXD1 PF10/RTS1/TIO0_6 PF11/CTS1 UART1 VTU0 X2CKI X2CKO 32.768 kHz Crystal VCC RESET X1CKI X1CKO IOVCC XD[15:0] PE0/RXD0/TIO0_1 PE1/TXD0 ENV1/TSTCLK1 CP3SP33MR (FBGA-144) 12 MHz Crystal or External Clock Input PE5/TA0/NMI ENV0/TSTCLK0 PE8/MSK0 PE9/MDIDO0 PE10/MDODI0 PE11/MWCS0/TIO0_7 PH3/CAN0TX/TIO1_8 PE2/RTS0/TIO0_3 PE3/CTS0 D- D+ TMS TDI TDO TCK RDY XCS0 XCS1 XOE XWE XBE[1:0] CPU JTAG Interface GND Operating Environment UVCC UGND PLLVCC PLLGND XA[20:0] USART0/ VTU0 Microwire /Plus SPI 0 NMI ADC ADC[1:0] PE6/CAN1RX PE7/CAN1TX PH2/CAN0RX/TIO1_7 PE13/IDPULLUP/TIO1_1 PE14/DRVVBUS/TIO1_3 IOGND ADVCC ADGND TCADCVCC TCADCGND TCDACVCC TCDACGND TCVCM1 TCMIC1P,TCMIC1N TCMIC2P,TCMIC2N TCLP,TCLN TCRP,TCRN TCVCM2 TCVBUF1 TCVBUF2 TCVRFP TCVRFN VBUS PE15/IDDIG/TIO1_5 RFVCC RFGND CLKIN/RFCK External Bus Interface USB Codec RF Interface CAN0 CAN1 Power Supply / 4 / 2 / 4 / 6 / 6 / 16 / 21 / 2 Reset PH1/SDA0/TIO1_6 PE12/SCL0/TIO0_5 ACCESS.bus 0 PG0/I2SCLK PG1/I2SWS PG2/I2SSDI PG3/I2SSDO I2 S PH[10:7] WUI / 4 / 2 / 2 / 2 / 2 PF1/SCLK RFDATA PF0/RFSYNC RFCE PF3/SLE PF4/BTSEQ1 PF2/SDAT PF8/RXD1/TIO0_4 PF9/TXD1 PF10/RTS1/TIO0_6 PF11/CTS1 UART1 VTU0 CP3SP33 www.ti.com SNOSCW5 – MAY 2013 4 Signal Descriptions Figure 4-1. CP3SP33 Device Signals Some pins may be enabled as general-purpose I/O-port pins or as alternate functions associated with specific peripherals or interfaces. These pins may be individually configured as port pins, even when the associated peripheral or interface is enabled. Table 4-1 describes the device signals. When the number of signals differs between packages, the first number in the Pins column is for the FBGA-224 package and the second number is for the FBGA-144 package. Copyright © 2013, Texas Instruments Incorporated Signal Descriptions 13 Submit Documentation Feedback Product Folder Links :CP3SP33 |
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