CP3SP33SMSSLASHNOPB datasheet(97/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

Table 16-2. Module Activity Summary (continued)

POWER MODE

MODULE

CLOCK SOURCE(s)

ACTIVE

POWER SAVE

IDLE

HALT

I2S Interface

On/Off

Off

Aux Clk 5, PCLK Clock, TCIO1

USB

On/Off

Off

Aux Clk 6

DSP

On/Off

Off

Aux Clk 7

AAI

On/Off

Off

Aux Clk 1, Aux Clk 8

All Others

On/Off

Off

HCLK Clock, PCLK Clock

A module shown as On/Off in Table 16-2 may be enabled or disabled by software. A module shown as

Active continues to operate even while its clock is suspended, which allows wake-up events to be

processed during Idle and Halt modes.

16.1 Active Mode

In Active mode, the high-frequency oscillator is active and generates the 12-MHz Main Clock. If the PLL

Clocks are not needed, the PLLs may remain powered off. Most devices on the CPU core bus are driven

by HCLK Clock, and most APB bus devices are driven by PCLK Clock.

When entering Active mode from a mode in which the high-frequency oscillator, PLLs, or low-frequency

clock were powered down, the mode switch will be stalled until the high-frequency oscillator, any enabled

PLL, and the low-frequency oscillator (if enabled) are producing stable clocks.

The activity of peripheral modules is controlled by their enable bits. Power consumption can be reduced in

Active mode by selectively disabling modules and by executing the WAIT instruction. When the WAIT

instruction is executed, the CPU stops executing new instructions until it receives an interrupt signal.

16.2 Power Save Mode

In Power Save mode, Slow Clock is used as the HCLK Clock which drives the CPU and core bus

modules. Power Save mode is intended for applications in which a low level of processing is required

during low-power standby, for example if software needs to detect events for which no hardware wake-up

signal is available.

If Slow Clock is driven by the 32.768 kHz oscillator and no on-chip module currently requires the 12-MHz

Main Clock, software can disable the high-frequency oscillator to further reduce power consumption. The

auxiliary clocks can be turned off under software control before switching to a reduced power mode, or

they may remain active as long as they have an active clock source.

If a PLL Clock is not used to generate HCLK Clock or an auxiliary clock, the corresponding PLL can be

powered down. Control over whether Main Clock and the PLLs are running can be controlled by the

Bluetooth controller through the Hardware Clock Control function (described in Section ), if enabled.

In Power Save mode, some modules are disabled or their operation is restricted. Other modules, including

the CPU, continue to function normally, but operate at a reduced clock rate. See the module descriptions

for details of each module’s activity in Power Save mode.

16.3 Idle Mode

In Idle mode, the HCLK Clock and PCLK Clock are disabled and therefore the clock is stopped to most

modules of the device. Idle mode is intended for applications in which no processing is required during

low-power standby, but the capability is needed to break out of the mode due to activity on the Bluetooth

interface or expiration of the watchdog timer. Idle mode can only be entered from Power Save mode.

Power Management Module

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