CP3SP33SMSSLASHNOPB datasheet(80/407 Pages) TI1

80 / 407 page

32.768 kHz

Crystal

GND

X2CKI

X2CKO

DS327

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

Figure 14-3. 32.768 kHz Oscillator Crystal Network

Table 14-2. 32.768 kHz Oscillator Component Values

SYMBOL

COMPONENT

PARAMETER

MIN

TYP

MAX

Crystal

Resonant Frequency

32.768 kHz

Crystal

Motional Resistance

1.7 pF

Crystal

Motional Resistance (ESR)

65 k

Crystal

Shunt Capacitance

1.3 pF

Crystal

Q Factor

40000

Capacitors

Load Capacitance

25 pF

14.2 Main Clock

Main Clock is generated by the 12-MHz high-frequency oscillator or driven by an external signal (typically

the LMX5251 or LMX5252 Bluetooth radio chip). It can be stopped by the Power Management Module to

reduce power consumption during periods of reduced activity. When the Main Clock is started or restarted,

a 14-bit timer generates a start-up delay to determine when the high-frequency oscillator is stable.

An external clock can be driven on the X1CKI input, but it must not exceed 1.8V. Alternatively, a 3.3V

external clock can be driven on the CLKIN pin, in which case the X1CKI input must be tied low. The

frequency must be a multiple of 12 MHz, up to 96 MHz. (If a frequency other than 12 MHz is chosen, the

timing of the external bus must be compatible with the external memory device used to boot up the

system.) If the Power Management Module indicates the high-frequency oscillator should be stopped, the

on-chip Main Clock signal is stopped even if it was driven by an external clock signal on CLKIN or X1CKI

that continues toggling.

14.3 Slow Clock

Slow Clock is necessary for operating the device in reduced power modes and to provide a clock source

for modules such as the Timing and Watchdog Module.

The low-frequency oscillator may be used to generate Slow Clock in a manner similar to the Main Clock. It

can be stopped by the Power Management Module to reduce power consumption during periods of

reduced activity. When the Slow Clock is started or restarted, a 6-bit timer generates a start-up delay to

determine when the low-frequency oscillator is stable.

Clock Generation

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