CP3SP33SMSSLASHNOPB datasheet(49/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

10.4.1 Static Memory Control Register (SMCTLR)

The SMCTLR register is a 32-bit, read/write register that selects the bus width of the memory devices

associated with the chip selects. At reset, the register is initialized to 0000 0401h, which selects 16-bit

width for XCS2 and XCS0, and 32-bit width for XCS1. The register format is shown below.

16M M15

13M M12

10M M9

7M M6

Reserved

SM_DW_S2

SM_DW_S1

SM_DW_S0

Reserved

SM_DW_S0

The Static Memory Data Bus Width field selects the width of the XCS0 device.

000 – 16 bits.

001 – 32 bits.

100 – 8 bits.

SM_DW_S1

The Static Memory Data Bus Width field selects the width of the XCS1 device.

000 – 16 bits.

001 – 32 bits.

100 – 8 bits.

SM_DW_S2

The Static Memory Data Bus Width field selects the width of the XCS2 device.

000 – 16 bits.

001 – 32 bits.

100 – 8 bits.

10.4.2 Chip Select Register n (SCSLRn)

The SCSLRn registers are 32-bit, read/write registers that specify base addresses for the chip selects.

Only bits 31:16 can be used, because the minimum memory device size is 64K bytes. Additional bits are

masked off if the size exceeds 64K. At reset, the SCSLR0 register is initialized to 0040 0000h, SCSLR1 is

initialized to 0080 0000h, and SCSLR2 is initialized to 0100 0000h. The register format is shown below.

16M M15

EXT_BASE_ADDR

Reserved

EXT_BASE_ADDR The External Base Address field specifies the base address of the external memory

device enabled by the chip select.

External Bus Interface Unit

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