CP3SP33SMSSLASHNOPB datasheet(74/407 Pages) TI1

74 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

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IEN2

Each Interrupt Enable bit enables or disables the corresponding interrupt channels IRQ64

through IRQ70.

0 – Interrupt is disabled.

1 – Interrupt is enabled.

13.6.7 Interrupt Status Register 0 (ISTR0)

The ISTR0 register is a 32-bit, read-only register. It indicates which maskable interrupt inputs IRQ31 to

IRQ1 are active. These bits are not affected by the state of the corresponding IENR0 bits. Because the

IRQ0 interrupt is not used, bit 0 always reads as 0.

IST0

Reserved

IST0

The Interrupt Status bits indicate if a maskable interrupt source is signAling an interrupt request.

0 – Interrupt is not active.

1 – Interrupt is active.

13.6.8 Interrupt Status Register 1 (ISTR1)

The ISTR1 register is a 32-bit, read-only register. It indicates which maskable interrupt inputs IRQ63 to

IRQ31 are active. These bits are not affected by the state of the corresponding IENR1 bits.

IST1

IST1 The Interrupt Status bits indicate if a maskable interrupt source is signaling an interrupt request.

0 – Interrupt is not active.

1 – Interrupt is active.

13.6.9 Interrupt Status Register 2 (ISTR2)

The ISTR2 register is a 32-bit, read-only register. It indicates which maskable interrupt inputs IRQ70 to

IRQ64 are active. These bits are not affected by the state of the corresponding IENR2 bits. Only bits 6:0

of this register are used.

IST2

The Interrupt Status bits indicate if a maskable interrupt source is signaling an interrupt

request.

0 – Interrupt is not active.

1 – Interrupt is active.

13.6.10 Software Interrupt Register 0 (SOFTR0)

The SOFTR0 register is a 32-bit, read/write register. Setting a bit in this register activates the

corresponding maskable interrupt IRQ31 to IRQ1. Bit 0 of this register is reserved. The register is

initialized to 0000 0000h at reset.

SOFT0

Reserved

Interrupts

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