CP3SP33SMSSLASHNOPB datasheet(7/407 Pages) TI1

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CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

Device Overview

The CP3SP33 connectivity processor is an advanced microcomputer with system timing, interrupt logic,

instruction cache, data memory, and I/O ports included on-chip, making it well-suited to a wide range of

embedded applications. The Section 2.1 shows the major on-chip components of the CP3SP33.

3.1

CR16CPlus CPU Core

The CP3SP33 contains a CR16CPlus CPU core. This core improves upon the performance of previous

CP3000 devices by adding a 4-Kbyte instruction cache and doubling the CPU core data bus bandwidth.

The cache greatly reduces instruction-fetch bandwidth on the 32-bit system bus, which leaves more bus

bandwidth available for DMA-based I/O. The cache moves the average execution rate closer to the peak

rate of one instruction per clock cycle, especially when executing from off-chip program memory. The

DMA controller provides efficient sharing of the CPU core bus between the CPU and high-bandwidth

peripherals such as wired and wireless communication interfaces.

For information on the instruction set architecture, refer to the CR16C Programmer’s Reference Manual

(document number 424521772-101, which may be downloaded from Texas Instruments web site at

http://www.ti.com).

3.2

Teak DSP Core

The Teak 16-bit fixed-point DSP core is designed for lowpower, high-speed digital signal processing

applications, including acoustic echo cancellation, noise reduction, and MP3/WMA decoding. It features a

four-bus, dual-MAC, enhanced Harvard architecture. The DSP has 24K bytes of dedicated program RAM,

24K bytes of data RAM, and a 4K-byte RAM shared with the CPU. The DSP has a bus master interface to

the 4K-byte shared RAM and an external memory bus. It also has a bus master interface to a shared

audio peripheral bus. The DSP is slave on the CPU peripheral bus, for downloading software to the

program RAM.

The DSP has its own DMA controller for I/O and memory access.

3.3

AMBA Bus Architecture

The CPU and DSP core buses implement AMBA-compatible AHB high-performance 32-bit buses with

bursting and split transactions. The CPU peripheral bus and CPU/DSP shared audio peripheral bus

implement AMBA-compatible 32-bit APB buses. The CPU and DSP buses operate at independent rates

up to 96 MHz. The APB buses operate at a rate which is a factor of 1, 2, or 4 slower than the CPU AHB

bus.

3.4

External Bus Interface Unit

The External Bus Interface Unit (EBIU) provides programmable timing, memory type, base address, size,

and bus width (8, 16, or 32 bits) for three regions of up to 32M bytes. An 8-level write buffer releases the

bus master to continue execution without waiting for write cycles to complete.

3.5

Memory

The CP3SP33 devices support a uniform linear address space. Three types of on-chip memory occupy

specific regions within this address space, along with any external memory:

•

32K bytes of CPU RAM

•

4K bytes of CPU/DSP shared RAM

•

8K bytes of Bluetooth sequencer and data RAM

•

Up to 96M bytes of external memory

A non-volatile external program memory is used to store the application program, Bluetooth protocol stack,

and real-time operating system.

Device Overview

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