CP3SP33SMSSLASHNOPB datasheet(28/407 Pages) TI1

28 / 407 page

Line 0

Entry 0

Entry 1

Entry 2

Entry 3

Line 1

Entry 4

Entry 5

Entry 6

Entry 7

Line 63

Entry 252

Entry 253

Entry 254

Entry 255

Way 0

Way 1

Way 2

Way 3

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

Table 6-1. CP3SP33 Memory Map (continued)

START ADDRESS

END ADDRESS

SIZE IN BYTES

DESCRIPTION

00FF C400h

00FF C7FFh

Port E

00FF C800h

00FF CBFFh

Port F

00FF CC00h

00FF CFFFh

Port H

00FF D000h

00FF EBFFh

Reserved

00FF EC00h

00FF EFFFh

Teak Access Port

00FF F000h

00FF F3FFh

Reserved

00FF F400h

00FF F7FFh

System Configuration

00FF F800h

00FF FBFFh

Reserved

00FF FC00h

00FF FFFFh

Interrupt Control Unit (registers start at 00FF FE00h)

0100 0000h

FFFF FFFFh

4G 16M

Available for External Bus Devices (data space only)

Instruction Cache

The CPU instruction cache has the following features:

•

4K bytes data memory

•

4-way set-associative organization

•

Critical word first, with wrapping cache entry fill

•

Pseudo Least Recently Used (PLRU) allocation policy

•

Cache locking support

•

Cache invalidation support

The instruction cache is enabled by setting the IC bit in the CFG register. At reset, the cache is disabled

by default. When caching is enabled, the instruction cache greatly accelerates program execution by

satisfying most instruction fetches. It also greatly reduces bus traffic to external memory, which increases

the bandwidth available for the DMA controllers and DSP.

The cache is organized as four ways of 64 entries each, as shown in Figure 7-1. Each entry holds 16 data

bytes (8 instructions).

Figure 7-1. CPU Instruction Cache Organization

Each entry consists of:

•

Valid Bit—Indicates whether the entry holds valid data. The valid bit is cleared when the cache is

disabled, when the CINV [i] instruction is executed, and at reset. The valid bit is set when the entry is

loaded.

•

Address Tag—Holds address bits 31:10 associated with the entry. The address tag is loaded when a

cache entry is allocated on a cache miss.

•

Data—Eight bytes of data. The data is passed to the CPU on a cache hit, and it is loaded when a

cache entry is allocated on a cache miss.

Instruction Cache

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