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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CP3SP33SMS/NOPB датащи(PDF) 3 Page - Texas Instruments |
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CP3SP33SMS/NOPB датащи(HTML) 3 Page - Texas Instruments |
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3 / 407 page  CP3SP33 www.ti.com SNOSCW5 – MAY 2013 1 Introduction .............................................. 1 10.2 Default Memory Configuration ...................... 44 1.1 Features ............................................. 1 10.3 External Bus Cycle Timing ......................... 45 1.2 CP3SP33 Connectivity Processor Selection Guide . 2 10.4 EBIU Registers ..................................... 48 2 Description ............................................... 6 10.5 Usage Notes ........................................ 52 2.1 Block Diagram ....................................... 6 11 System Configuration ................................ 52 3 Device Overview ........................................ 7 11.1 Operating Environment ............................. 52 3.1 CR16CPlus CPU Core ............................... 7 11.2 Freeze Mode ....................................... 52 3.2 Teak DSP Core ...................................... 7 11.3 System Configuration Registers .................... 53 3.3 AMBA Bus Architecture .............................. 7 11.4 Module Configuration Register (MCFG) ............ 53 3.4 External Bus Interface Unit .......................... 7 11.5 Module Status Register (MSTAT) .................. 54 3.5 Memory .............................................. 7 11.6 Software Reset Register (SWRESET) ............. 54 3.6 Bluetooth LLC ........................................ 8 11.7 System Configuration Register (SYSCFG) ......... 54 3.7 USB .................................................. 8 12 CPU DMA Controller .................................. 55 3.8 CAN Interface ........................................ 8 12.1 DMA-Capable Peripherals .......................... 56 3.9 Audio/Telematics Codec ............................. 9 12.2 Transfer Types ..................................... 57 3.10 CVSD/PCM Conversion Modules .................... 9 12.3 Transfer Modes ..................................... 58 3.11 I2S Digital Audio Bus ................................ 9 12.4 Software DMA Request ............................ 60 3.12 Advanced Audio Interface ........................... 9 12.5 DMA Request Timeout ............................. 61 3.13 Analog to Digital Converter .......................... 9 12.6 Error Response ..................................... 61 3.14 Quad UART ........................................ 10 12.7 Freeze Mode ....................................... 61 3.15 Microwire/SPI ....................................... 10 12.8 Register Programming ............................. 61 3.16 Dual ACCESS.BUS Interface ...................... 10 12.9 DMA Controller Register Set ....................... 61 3.17 Dual Multi-Function Timer .......................... 10 13 Interrupts ................................................ 68 3.18 Versatile Timer Units ............................... 11 13.1 Non-Maskable Interrupts ........................... 68 3.19 Timing and Watchdog Module ..................... 11 13.2 Maskable Interrupts ................................. 68 3.20 Power Management ................................ 11 13.3 Interrupt Priority Groups ............................ 70 3.21 Multi-Input Wake-up ................................ 11 13.4 Nested Interrupts ................................... 71 3.22 Input/Output Ports .................................. 11 13.5 Software Interrupts ................................. 71 3.23 Clock and Reset Module ........................... 11 13.6 Interrupt Controller Registers ....................... 71 3.24 DMA Controller ..................................... 12 13.7 Usage Notes ........................................ 77 3.25 Serial Debug Interface ............................. 12 14 Clock Generation ...................................... 77 3.26 Development Support .............................. 12 14.1 Extrnal Crystal Networks ........................... 78 4 Signal Descriptions ................................... 13 14.2 Main Clock .......................................... 80 5 CPU Architecture ...................................... 18 14.3 Slow Clock .......................................... 80 5.1 General-Purpose Registers ........................ 18 14.4 PLL Clocks ......................................... 81 5.2 Dedicated Address Registers ...................... 19 14.5 HCLK Clock ........................................ 84 5.3 Processor Status Register (PSR) .................. 19 14.6 PCLK Clock ........................................ 84 5.4 Configuration Register (CFG) ...................... 21 14.7 Auxiliary Clocks .................................... 84 5.5 Addressing Modes .................................. 21 14.8 Clock Generation Registers ........................ 87 5.6 Stacks .............................................. 23 15 Reset ..................................................... 92 5.7 Instruction Set ...................................... 23 15.1 Power-On Reset .................................... 92 6 Memory .................................................. 27 15.2 Reset Input Timing ................................. 92 7 Instruction Cache ...................................... 28 16 Power Management Module ......................... 96 7.1 Cache Locking ...................................... 29 16.1 Active Mode ........................................ 97 7.2 Cache Invalidation .................................. 30 16.2 Power Save Mode .................................. 97 8 CPU Core Bus Arbitration ........................... 30 16.3 Idle Mode ........................................... 97 8.1 Bus Arbiter Registers ............................... 31 16.4 Halt Mode .......................................... 98 9 DSP and Audio Peripherals ......................... 32 16.5 Hardware Clock Control ............................ 98 9.1 DSP Memory Spaces .............................. 34 16.6 Switching Between Power Modes .................. 98 9.2 CPU/DSP Interface ................................. 34 16.7 Power Management Register ..................... 101 9.3 DSP and ASC Registers ........................... 37 17 Multi-Input Wake-Up ................................. 103 10 External Bus Interface Unit .......................... 44 17.1 Multi-Input Wake-Up Registers .................... 105 10.1 External Bus Signals ............................... 44 18 Input/Output Ports ................................... 109 Copyright © 2013, Texas Instruments Incorporated Contents 3 Submit Documentation Feedback Product Folder Links :CP3SP33 |
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