CP3SP33SMSSLASHNOPB datasheet(21/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

5.4

Configuration Register (CFG)

The CFG register is used to enable or disable various operating modes and to control optional on-chip

caches. All CFG bits are cleared on reset.

Reserved

LIC

Reserved

The Instruction Cache bit controls whether the 4K-byte instruction cache is enabled for satifying

instruction fetches by the CPU. When the instruction cache is disabled, every instruction fetch is

propagated to the CPU core bus. Disabling the cache automatically invalidates all of the cache

entries. When the cache is enabled, instruction fetches that are cache hits do not result in bus

cycles on the CPU core bus.

0 – Instruction cache disabled.

1 – Instruction cache enabled.

LIC

The Lock Instruction Cache bit controls whether the 4K-byte instruction cache is locked. When the

instruction cache is locked, no new entries are allocated as a result of cache misses, however

cache hits continue to be handled by the cache.

0 – Instruction cache is not locked.

1 – Instruction cache is locked.

The Extended Dispatch bit selects whether the size of an entry in the interrupt dispatch table (IDT)

is 16 or 32 bits. Each entry holds the address of the appropriate exception handler. When the IDT

has 16-bit entries, and all exception handlers must reside in the first 128K of the address space.

The location of the IDT is held in the INTBASE register, which is not affected by the state of the

ED bit.

0 – Interrupt dispatch table has 16-bit entries.

1 – Interrupt dispatch table has 32-bit entries.

The Short Register bit enables a compatibility mode for the CR16B large model. In the CR16CPlus

core, registers R12, R13, and RA are extended to 32 bits. In the CR16B large model, only the

lower 16 bits of these registers are used, and these “short registers” are paired together for 32-bit

operations. In this mode, the (RA, R13) register pair is used as the extended RA register, and

address displacements relative to a single register are supported with offsets of 0 and 14 bits in

place of the index addressing with these displacements.

0 – 32-bit registers are used.

1 – 16-bit registers are used (CR16B mode).

5.5

Addressing Modes

The CR16CPlus CPU core implements a load/store architecture, in which arithmetic and logical

instructions operate on register operands. Memory operands are made accessible in registers using load

and store instructions. For effIcient implementation of I/O-intensive embedded applications, the

architecture also provides a set of bit operations that operate on memory operands.

The load and store instructions support these addressing modes: register/pair, immediate, relative,

absolute, and index addressing. When register pairs are used, the lower bits are in the lower index

registers R12, R13, RA, and SP are also treated as register pairs.

References to register pairs in assembly language use parentheses. With a register pair, the lower

numbered register pair must be on the right. For example,

jump (r5, r4)

load $4(r4,r3), (r6,r5)

load $5(r12), (r13)

The instruction set supports the following addressing modes:

CPU Architecture

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