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CP3SP33SMS/NOPB датащи(PDF) 63 Page - Texas Instruments

номер детали CP3SP33SMS/NOPB
подробное описание детали  Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces
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CP3SP33SMS/NOPB датащи(HTML) 63 Page - Texas Instruments

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SNOSCW5 – MAY 2013
Table 12-4. DMA Controller Registers (continued)
Name
Address
Description
Name
Address
Description
DMACNT9
FF 0660h
DMA Control Register
BLTC13
FF 0750h
Block Length Counter Register
DMASTAT9
FF 0664h
DMA Status Register
BLTR13
FF 0754h
Block Length Register
ADCA10
FF 0680h
Device A Address Counter Register
RQTR13
FF 0758h
Request Timeout Register
ADRA10
FF 0684h
Device A Address Register
RQTCNT13
FF 075Ch
Request Timeout Counter Register
ADCB10
FF 0688h
Device B Address Counter Register
DMACNT13
FF 0760h
DMA Control Register
ADRB10
FF 068Ch
Device B Address Register
DMASTAT13
FF 0764h
DMA Status Register
BLTC10
FF 0690h
Block Length Counter Register
ADCA14
FF 0780h
Device A Address Counter Register
BLTR10
FF 0694h
Block Length Register
ADRA14
FF 0784h
Device A Address Register
RQTR10
FF 0698h
Request Timeout Register
ADCB14
FF 0788h
Device B Address Counter Register
RQTCNT10
FF 069Ch
Request Timeout Counter Register
ADRB14
FF 078Ch
Device B Address Register
DMACNT10
FF 06A0h
DMA Control Register
BLTC14
FF 0790h
Block Length Counter Register
DMASTAT10
FF 06A4h
DMA Status Register
BLTR14
FF 0794h
Block Length Register
ADCA11
FF 06C0h
Device A Address Counter Register
RQTR14
FF 0798h
Request Timeout Register
ADRA11
FF 06C4h
Device A Address Register
RQTCNT14
FF 079Ch
Request Timeout Counter Register
ADCB11
FF 06C8h
Device B Address Counter Register
DMACNT14
FF 07A0h
DMA Control Register
ADRB11
FF 06CCh
Device B Address Register
DMASTAT14
FF 07A4h
DMA Status Register
BLTC11
FF 06D0h
Block Length Counter Register
ADRA15
FF 07C4h
Device A Address Register
BLTR11
FF 06D4h
Block Length Register
ADCB15
FF 07C8h
Device B Address Counter Register
RQTR11
FF 06D8h
Request Timeout Register
ADRB15
FF 07CCh
Device B Address Register
RQTCNT11
FF 06DCh
Request Timeout Counter Register
BLTC15
FF 07D0h
Block Length Counter Register
DMACNT11
FF 06E0h
DMA Control Register
BLTR15
FF 07D4h
Block Length Register
DMASTAT11
FF 06E4h
DMA Status Register
RQTR15
FF 07D8h
Request Timeout Register
ADCA12
FF 0700h
Device A Address Counter Register
RQTCNT15
FF 07DCh
Request Timeout Counter Register
ADRA12
FF 0704h
Device A Address Register
DMACNT15
FF 07E0h
DMA Control Register
ADCA15
FF 07C0h
Device A Address Counter Register
DMASTAT15
FF 07E4h
DMA Status Register
12.9.1 Device A Address Counter Register n (ADCAn)
The Device A Address Counter register is a 32-bit, read/ write register. It holds the current address of
either the source data item or the destination location, depending on the state of the DIR bit in the
DMACNTn register. The ADA bit of DMACNTn register controls whether to adjust the pointer in the
ADCAn register by the step size specified in the INCA field of DMACNTn register.
31
0
Device A Address Counter
12.9.2 Device A Address Register n (ADRAn)
The Device A Address register is a 32-bit, read/write register. It holds the starting address of either the
next source data block, or the next destination data area, according to the DIR bit in the DMACNTn
register.
31
0
Device A Address
12.9.3 Device B Address Counter Register n (ADCBn)
The Device B Address Counter register is a 32-bit, read/ write register. It holds the address of either the
source data item, or the destination location, according to the DIR bit in the DMACNTn register. The
ADCBn register is updated after each transfer cycle by INCB field of the DMACNTn register according to
ADB bit of the DMACNTn register.
Copyright © 2013, Texas Instruments Incorporated
CPU DMA Controller
63
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