CP3SP33SMSSLASHNOPB datasheet(95/407 Pages) TI1

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GND

IOVCC

DS493

CP3SP33

IOVCC

RESET

LM3710

Supervisory

Circuit with

Power-Fail

and Low-Line

Detection

Manual

Reset

NMI

IRQ

Core VCC

(1.8V)

VCC

GPIO

Reset Output

Power Fail Output (PFO)

Low Line Output (LLO)

Watchdog Input (WDI)

Power Fail

Input (PFI)

N Ÿ

CP3SP33

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SNOSCW5 – MAY 2013

15.2.3 Fault-Tolerant External Reset

An external reset circuit based on the LM3710 Microprocessor Supervisory Circuit is shown in

Figure 15-4. It provides a high level of fault tolerance in that it provides the ability to monitor both the VCC

supply for the core logic and the IO-VCC supply. It also provides a low-voltage indication for the IOVCC

supply and an external watchdog timer.

Figure 15-4. Fault-Tolerant External Reset

The signals shown in Figure 15-4 are:

•

Core VCC—the 1.8V power supply rail for the core logic.

•

IOVCC—the 3.0–3.3V power supply rail for the I/O logic.

•

Watchdog Input (WDI)—this signal is asserted by the CP3SP33 at regular intervals to indicate normal

operation. A general-purpose I/O (GPIO) port may be used to provide this signal. If the internal

watchdog timer in the CP3SP33 is used, then the LM3704 Microprocessor Supervisory Circuit can

provide the same features as the LM3710 but without the watchdog timer.

•

RESET—an active-low reset signal to the CP3SP33. The LM3710 is available in versions with active

pullup or an open-drain RESET output.

•

Power-Fail Input (PFI)—this is a voltage level derived from the Core VCC power supply rail through a

simple resistor divider network.

•

Power-Fail Output (PFO)—this signal is asserted when the voltage on PFI falls below 1.225V. PFO is

connected to the non-maskable interrupt (NMI) input on the CP3SP33. A system shutdown routine can

then be invoked by the NMI handler.

•

Low Line Output (LLO)—this signal is asserted when the main IOVCC level fails below a warning

threshold voltage but remains above a reset detection threshold. This signal may be routed to the NMI

input on the CP3SP33 or to a separate interrupt input.

These additional status and feedback mechanisms allow the CP3SP33 to recover from software hangs or

perform system shutdown functions before being placed into reset.

The standard reset threshold for the LM3710 is 3.08V with other options for different watchdog timeout

and reset timeouts. The selection of these values are much more application-specific. The combination of

a watchdog timeout period of 1600 ms and a reset period of 200 ms is a reasonable starting point.

Reset

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