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CP3SP33SMS/NOPB датащи(PDF) 45 Page - Texas Instruments

номер детали CP3SP33SMS/NOPB
подробное описание детали  Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces
PDF  407 Pages
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производитель  TI1 [Texas Instruments]
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CP3SP33SMS/NOPB датащи(HTML) 45 Page - Texas Instruments

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XCSn
HCLK
DS414
tRC
XAn
XOE
XBEn
XDn
Data
Address
CP3SP33
www.ti.com
SNOSCW5 – MAY 2013
Table 10-2. Default Memory Configuration
CHIP SELECT
PARAMETER
XCS2
XCS1
XCS0
Memory Type
RAM
RAM
RAM
Base Address
0100 0000h
0080 0000h
0040 0000h
Memory Size
16M Bytes
8M Bytes
8M Bytes
Memory Width
16 Bits
32 Bits
16 Bits
Read Cycle Time
22 Cycles
22 Cycles
22 Cycles
RAM Write Address Setup Time
1 Cycle
1 Cycle
1 Cycle
RAM Write Address and Data Hold Time
1 Cycle
1 Cycle
1 Cycle
RAM Write Pulse Width
4 Cycles
4 Cycles
4 Cycles
Bus Turnaround Time
2 Cycles
2 Cycles
2 Cycles
Page-Mode
Disabled
Disabled
Disabled
Page-Mode Read Cycle Time
4 Cycles
3 Cycles
1 Cycle
Page Size
4 Words
4 Words
4 Words
Memory Read Pipe Stages
0
0
0
10.3 External Bus Cycle Timing
Figure 10-1 shows the timing of a read cycle on the external memory bus.
Figure 10-1. Read Cycle Timing
Copyright © 2013, Texas Instruments Incorporated
External Bus Interface Unit
45
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